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		    <title>PatentStorm -&gt; Patents -&gt; Electricity: conductors and insulators</title>
		    <link>http://www.patentstorm.us/rss/class/patents/rss-174.xml</link>
		    <description>Recent patents filings in USPTO Class 174 Electricity: conductors and insulators.</description>
		    <pubDate>Tue, 7 Feb 2012 16:03:07</pubDate>
		    <managingEditor>patents@patentstorm.us</managingEditor>
		    <language>en</language><atom10:link xmlns:atom10="http://www.w3.org/2005/Atom" rel="self" type="application/rss+xml" href="http://feeds.feedburner.com/Patentstorm-Patents-ElectricityConductorsAndInsulators" /><feedburner:info uri="patentstorm-patents-electricityconductorsandinsulators" /><atom10:link xmlns:atom10="http://www.w3.org/2005/Atom" rel="hub" href="http://pubsubhubbub.appspot.com/" /><item>
			         <title><![CDATA[Receptacle with shaped surface]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/RlXiKo7EXes/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;RE43156&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Oddsen, Dennis A.; Zacharevitz, Steve; Lindenstraus, Leslie&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;The instant invention discloses a receptacle where the surface of the face along its width is flat in one plane and along its length has a constant radius. The shape of the face of the receptacle allows for the proper seating of an inserted plug. The receptacle is adapter to be located in a wall plate having a vertical axis of positive first differential and zero second differential, comprised of a combination of splines drawn between points of varying distance from a datum plane and zero ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/vcC_IGH_WSmCKE26lX-EYQzMdsI/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/vcC_IGH_WSmCKE26lX-EYQzMdsI/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/vcC_IGH_WSmCKE26lX-EYQzMdsI/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/vcC_IGH_WSmCKE26lX-EYQzMdsI/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/RlXiKo7EXes" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/RE43156/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Electronic device]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/PrMOaIfJrus/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110756&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Sawai, Jun; Miyahara, Munetoshi&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electronic device includes a housing and a positioning portion. The housing includes a first member secured to the housing and a second member secured to the first member. The positioning portion is configured to position the second member at a predetermined position relative to the first member when the second member is secured to the first member in an assembly process of the electronic ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/QHyNcV_-Bhnc5vE2yeGrlLlISvI/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/QHyNcV_-Bhnc5vE2yeGrlLlISvI/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/QHyNcV_-Bhnc5vE2yeGrlLlISvI/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/QHyNcV_-Bhnc5vE2yeGrlLlISvI/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/PrMOaIfJrus" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8110756/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Package for an optical device]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/pwISmsgfLio/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110755&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Takayama, Yoshiki&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A device includes: a package having a bottom and a side wall surrounding the bottom; an element adhered to the bottom of the package; an internal contact formed inside the package; a resin encapsulation material with which a space between the package and the element is filled; and a coating formed to cover an end surface of the internal contact near the element, and made of a material whose thermal expansion coefficient is greater than or equal to the thermal expansion coefficient of the ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/9I4L3WPdi7-TQXGYDNRwmV6cHyA/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/9I4L3WPdi7-TQXGYDNRwmV6cHyA/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/9I4L3WPdi7-TQXGYDNRwmV6cHyA/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/9I4L3WPdi7-TQXGYDNRwmV6cHyA/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/pwISmsgfLio" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Multi-layer wiring board and method of manufacturing the same]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/6WHnNNAz39s/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110754&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Asano, Toshiya&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A multi-layer wiring board without a core substrate includes: a multi-layer laminated structure; first terminals provided on a front surface of the multi-layer laminated structure; second terminals provided on a rear surface of the multi-layer laminated structure; terminal pins bonded to a corresponding one of the second terminals, wherein each of the terminal pins is formed in a nailhead shape that includes a shaft portion and a head portion, and a diameter of the head portion is larger ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/et1HdReLNLNTKKC8AeJGJtOYnSY/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/et1HdReLNLNTKKC8AeJGJtOYnSY/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/et1HdReLNLNTKKC8AeJGJtOYnSY/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/et1HdReLNLNTKKC8AeJGJtOYnSY/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/6WHnNNAz39s" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8110754/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Circuit board assembly]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/-KnVUD_U0RM/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110753&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Chen, Wei-Cheng; Liao, Cheng-Chao&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A circuit board assembly includes: a circuit board having opposite first and second surfaces and formed with a first through-hole defined by a hole-defining wall that extends between and that terminates at the first and second surfaces and that cooperates with the first and second surfaces to define first and second turns, respectively, the circuit board further having an abutting wall that extends between and that terminates at the first and second surfaces and that cooperates with the ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/Dlr8AUcHF8TGvVbxLVGnK_YEX5E/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/Dlr8AUcHF8TGvVbxLVGnK_YEX5E/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/Dlr8AUcHF8TGvVbxLVGnK_YEX5E/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/Dlr8AUcHF8TGvVbxLVGnK_YEX5E/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/-KnVUD_U0RM" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Wiring substrate and method for manufacturing the same]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/skYENwJvfR8/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110752&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Nagaya, Fusaji; Kuroda, Nobuhisa; Awano, Atsushi&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A method for manufacturing a wiring substrate includes forming a conductor circuit on an insulating layer, the conductor circuit including a pad, a circuit pattern connected to the pad, and a lead pattern connected to the pad. A solder resist layer is formed on the circuit pattern and on the insulating layer, and a plating resist layer is formed on the lead pattern and on the insulating layer and forming a metal film on a first portion of the conductor circuit not covered by the solder ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/tu4OSSca1tE20xkmuK8VviHJBDM/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/tu4OSSca1tE20xkmuK8VviHJBDM/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/tu4OSSca1tE20xkmuK8VviHJBDM/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/tu4OSSca1tE20xkmuK8VviHJBDM/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/skYENwJvfR8" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Semiconductor memory module and electronic component socket for coupling with the same]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/wy1ZBgLOfeo/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110751&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Kyeon, Yong Tae; Ku, Ja Yong; Kim, Dong You&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;The present invention relates to a semiconductor memory module and an electronic component socket for coupling with the same. A printed circuit board of the semiconductor memory module includes three signal pad arrays longitudinally formed in a row on one sides of a first surface, a second surface and a third surface thereof. Each signal pad array includes a plurality of signal pads. An electronic component socket for coupling with the printed circuit board includes thee pin arrays. Thus, ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/TUElCcdSjvDYfgEvPVP40OjI2Fg/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/TUElCcdSjvDYfgEvPVP40OjI2Fg/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/TUElCcdSjvDYfgEvPVP40OjI2Fg/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/TUElCcdSjvDYfgEvPVP40OjI2Fg/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/wy1ZBgLOfeo" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8110751/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Multilayer printed wiring board]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/A0oXuSunGXQ/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110750&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Inagaki, Yasushi; Sano, Katsuyuki&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A multilayer printed wiring board has a core substrate, an interlayer insulation layer formed over the core substrate, conductive layers formed over the core substrate, and a via hole for providing electrical connection between the conductive layers. The conductive layers include a conductive layer formed on the core substrate, and the conductive layer formed on the core substrate has a side face in a form of rounded taper tapering toward the core ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/GWA7ZA1IXqghK9OLFDVYXe4OMRY/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/GWA7ZA1IXqghK9OLFDVYXe4OMRY/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/GWA7ZA1IXqghK9OLFDVYXe4OMRY/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/GWA7ZA1IXqghK9OLFDVYXe4OMRY/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/A0oXuSunGXQ" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8110750/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Printed wiring board]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/7bxkgGuNdcE/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110749&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Abe, Tomoyuki; Hirano, Shin; Iida, Kenji; Maehara, Yasutomo; Yoshimura, Hideaki&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Large-sized through holes are formed in a core layer of a printed wiring board. Large-sized vias are formed in the shape of a cylinder along the inward wall surfaces of the large-sized through holes located within a specific area. A filling material fills the inner space of the large-sized via. A small-sized through hole penetrates through the corresponding filling material along the longitudinal axis of the small-sized through hole. A small-sized via is formed in the shape of a cylinder ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/CHCel4oNJ9OgolHLvSfsS2pnHD4/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/CHCel4oNJ9OgolHLvSfsS2pnHD4/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/CHCel4oNJ9OgolHLvSfsS2pnHD4/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/CHCel4oNJ9OgolHLvSfsS2pnHD4/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/7bxkgGuNdcE" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Wiring, display device and method of manufacturing the same]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/DD7EqHSwalY/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110748&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Nakamura, Hiroki&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;The present invention provides a wiring, a display device, and a method of manufacturing the same. A first metal diffusion-preventing layer is formed on a substrate or on a circuit element formed on the substrate. Then, a metal wiring layer is selectively formed on the first metal diffusion-preventing layer by an electroless metal plating method or a metal electroplating method. Further, the undesired portion of the first metal diffusion-preventing layer is removed. Finally, a second metal ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/DoROnJf2mZoEXs36lF9VQWv6zew/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/DoROnJf2mZoEXs36lF9VQWv6zew/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/DoROnJf2mZoEXs36lF9VQWv6zew/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/DoROnJf2mZoEXs36lF9VQWv6zew/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/DD7EqHSwalY" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8110748/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Flexible printed circuit board]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/ZsIH3gJd7AU/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110747&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Pai, Chia-Nan; Hsu, Shou-Kuo&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A flexible printed circuit board (FPCB) includes a signal layer, upper and lower ground layers, and two dielectric layers. The signal layer includes a differential pair comprising two transmission lines to transmit a pair of differential signals. The dielectric layers are located on and under the signal layer to sandwich the signal layer. The upper ground layer is attached to the dielectric layer on the signal layer, opposite to the signal layer. The lower ground layer is attached to the ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/yhuMHrEF-AYUzMS55a4gntJxYOc/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/yhuMHrEF-AYUzMS55a4gntJxYOc/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/yhuMHrEF-AYUzMS55a4gntJxYOc/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/yhuMHrEF-AYUzMS55a4gntJxYOc/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/ZsIH3gJd7AU" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8110747/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Cooling of substrate using interposer channels]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/lN5IfenN7iM/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110746&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Lu, Minhua; Mok, Lawrence S.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A structure. The structure includes an interposer adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The enclosure is made of a thermally conductive material. The cavity includes a thermally conductive foam material. The foam material includes pores and includes at least one serpentine channel. Each serpentine channel has at least two contiguously connected ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/jIOKev0bfSvp4M4sQcC4pEY7zGk/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/jIOKev0bfSvp4M4sQcC4pEY7zGk/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/jIOKev0bfSvp4M4sQcC4pEY7zGk/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/jIOKev0bfSvp4M4sQcC4pEY7zGk/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/lN5IfenN7iM" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8110746/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Flexible shielded cable]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/c5MKvop3Ago/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110744&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Wong, Suinin William; Lam, Cheung-Wei&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A flexible shielded cable is disclosed. The cable may include a plurality of conductors formed on a common base, a dielectric material disposed about the plurality of conductors, and a shielding material disposed adjacent the dielectric material. At least one of the plurality of conductors may include an unshielded portion not overlaid by the shielding material and at least one of the plurality of conductors may include a shielded portion overlaid by the shielding ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/mhz7ih7xkusZPfAwB3E5QKVeXkA/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/mhz7ih7xkusZPfAwB3E5QKVeXkA/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/mhz7ih7xkusZPfAwB3E5QKVeXkA/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/mhz7ih7xkusZPfAwB3E5QKVeXkA/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/c5MKvop3Ago" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8110744/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Electrical box cover with insect guard]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/ebFQNmDK5Wk/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110743&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Drane, Mark R.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electrical box cover including a housing and a hood pivotally attached to the housing and moveable between an open and closed position. The housing includes a base wall adapted to be attached to an electrical box. The base wall is surrounded by an outwardly extending side wall. The side wall includes a first opening defined by an edge. A guard having an opening formed therein is insertable over the first opening and securable to the side ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/7ck9jRxcyMcirDs4gq4PQ-KoXvQ/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/7ck9jRxcyMcirDs4gq4PQ-KoXvQ/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/7ck9jRxcyMcirDs4gq4PQ-KoXvQ/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/7ck9jRxcyMcirDs4gq4PQ-KoXvQ/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/ebFQNmDK5Wk" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8110743/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Temporary protective cover for an electrical box]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/NxKFkLkL2Fg/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110742&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Compagnone, Jr., Carlo&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A temporary protective cover for an electrical box having an open front end. In some embodiments of the invention, the cover is constructed for attachment directly to a circular type electrical box and includes a circular plate of plastic having a pair of flexible wings for use in securing the cover to the electrical box and a pair of punch-outs for use in securing the cover to the electrical box. In some other embodiments of the invention the cover is constructed for attachment to a ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/UtFknbcnZn2G07H0rEF4-zGdW1c/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/UtFknbcnZn2G07H0rEF4-zGdW1c/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/UtFknbcnZn2G07H0rEF4-zGdW1c/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/UtFknbcnZn2G07H0rEF4-zGdW1c/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/NxKFkLkL2Fg" height="1" width="1"/&gt;</description>
			         
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<item>
			         <title><![CDATA[Composite coiled tubing end connector]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/bnLwTSq6RZA/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8110741&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-02-07&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Brotzell, Arthur D.; Fowler, Stewart H.; Tho, Chanthol&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Connectors for attaching a composite pipe to a service member are described herein. In one embodiment, a connector can include a service end, a slip nut, a slip, a seal carrier, and an energy conductor. The slip nut can be disposed about the outer surface of the pipe and can be engaged by the service end. The slip can be positioned about the outer surface of the pipe and can be engaged by the service end and the slip nut to compress the slip into gripping contact with the pipe. The seal ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/6pbRDhQGIln1DP3IWUQ56LnFNSI/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/6pbRDhQGIln1DP3IWUQ56LnFNSI/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/6pbRDhQGIln1DP3IWUQ56LnFNSI/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/6pbRDhQGIln1DP3IWUQ56LnFNSI/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/bnLwTSq6RZA" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8110741/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Wire fitting]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/dNUqPC_nS5A/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106313&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Tremaine, John M&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;The present invention is directed to a wire fitting that may be used to pass a wire, cable or other conductor through a surface in order to produce a substantially secure and water tight connection between the wire fitting, the wire and the surface. The wire fitting may include a cap unit that is configured to be removably affixed to a base unit. The cap unit and the base unit may include corresponding threads to allow the cap unit to be screwed onto the base unit. A compressible plug may ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/l6nF6k8ob6Ml4OLBy9YaON074RQ/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/l6nF6k8ob6Ml4OLBy9YaON074RQ/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/l6nF6k8ob6Ml4OLBy9YaON074RQ/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/l6nF6k8ob6Ml4OLBy9YaON074RQ/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/dNUqPC_nS5A" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8106313</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8106313/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Sealing structure, electronic device, sealing method, gasket, and manufacturing method thereof]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/1ASdc8L8KI4/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106312&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Shinoda, Takao; Yamaguchi, Shingo; Hizuka, Hidehiko&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A sealing structure to seal housings includes a sealing member disposed between housings to be bonded to allow penetration of at least one signal line; and an adhesive material disposed between the signal lines penetrating the sealing member to bond the signal lines to be ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/P11ZOJ5rd37rw_RMjfif_b6naWo/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/P11ZOJ5rd37rw_RMjfif_b6naWo/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/P11ZOJ5rd37rw_RMjfif_b6naWo/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/P11ZOJ5rd37rw_RMjfif_b6naWo/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/1ASdc8L8KI4" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8106312</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8106312/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Cable pathway patch rack with waterfall member]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/wSyO3YrLPYs/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106311&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Levesque, Stewart A.; Larsen, Lars R.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A patch panel rack including a front face and an opening formed in the front face configured and dimensioned to receive and accommodate for mounting with respect to the patch panel rack at least one patch panel, further includes a waterfall member connected to the front face of the patch panel rack, the waterfall member including a horizontally extending surface positioned in front of the front face just below the opening formed therein, and at least one curved drop-off portion positioned ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/iMOD-98IxOgXPuIa32nIiJ68x0M/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/iMOD-98IxOgXPuIa32nIiJ68x0M/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/iMOD-98IxOgXPuIa32nIiJ68x0M/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/iMOD-98IxOgXPuIa32nIiJ68x0M/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/wSyO3YrLPYs" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/LvoRdtxjjew/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106310&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Satake, Hiroaki; Kawasaki, Yogo; Iwata, Yutaka; Tanabe, Tetsuya&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A multi-layer printed circuit board having interlayer resin insulating layers on both sides of a core substrate, respectively, through holes provided to penetrate the core substrate and filled with resin filler, the interlayer resin insulating layers and conductor circuits provided. The resin filler contains an epoxy resin, a curing agent and 10 to 50% of inorganic ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/_D_HSBTu0paxrhEleS9ibgIXCLw/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/_D_HSBTu0paxrhEleS9ibgIXCLw/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/_D_HSBTu0paxrhEleS9ibgIXCLw/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/_D_HSBTu0paxrhEleS9ibgIXCLw/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/LvoRdtxjjew" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Flexible printed circuit, display device including the same, and manufacturing method thereof]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/ShEio3etn4k/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106309&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Hwang, In-Yong&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A flexible printed circuit film includes a film including a first region of an adhesion region and a second region outside of the adhesion region, a signal wire formed on the second region, and reinforcement wiring connected to the signal wire and formed on the first region and the second region. The reinforcement wiring includes a bent portion having a plurality of inner corners and a plurality of outer corners, and the inner corners of the reinforcement wiring are spaced apart from a ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/4LzNSjID9NMdUoq1gWXzlm7b6tI/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/4LzNSjID9NMdUoq1gWXzlm7b6tI/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/4LzNSjID9NMdUoq1gWXzlm7b6tI/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/4LzNSjID9NMdUoq1gWXzlm7b6tI/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/ShEio3etn4k" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Printed circuit board for package and manufacturing method thereof]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/FaEqCMjH7FA/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106308&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Shin, Young-Hwan; Jeon, Hyung-Jin; Lee, Tae-Gon&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A printed circuit board for a package includes a first insulation layer, on one side of which an electronic component having a plurality of electrical contacts is mounted; a plurality of first bond pads formed on the other side of the first insulation layer in predetermined intervals, which are electrically connected with the electrical contacts; a second insulation layer stacked on the other side of the first insulation layer, with those portions removed where the first bond pads are ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/TFhkRxlSnanQYJE9zFPM_j3KtbY/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/TFhkRxlSnanQYJE9zFPM_j3KtbY/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/TFhkRxlSnanQYJE9zFPM_j3KtbY/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/TFhkRxlSnanQYJE9zFPM_j3KtbY/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/FaEqCMjH7FA" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8106308</guid>
			
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			         <title><![CDATA[Substrate structure and electronic apparatus]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/zl4I7aEM3Ks/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106307&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Yoshida, Mamoru; Hayakawa, Haruo; Konishi, Kazuhiro; Kouno, Kazunori&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A substrate structure capable of miniaturizing and thinning a housing of a portable terminal is provided.&lt;/p&gt;
&lt;p&gt;A substrate structure &lt;b&gt;10&lt;/b&gt; comprises a substrate &lt;b&gt;11&lt;/b&gt;, plural electronic components &lt;b&gt;12&lt;/b&gt; mounted along one mounting surface &lt;b&gt;11&lt;/b&gt;A in the substrate &lt;b&gt;11&lt;/b&gt;, and a resin part &lt;b&gt;13&lt;/b&gt; for making close contact with the mounting surface &lt;b&gt;11&lt;/b&gt;A of the substrate &lt;b&gt;11&lt;/b&gt;while each of the electronic components &lt;b&gt;12&lt;/b&gt; is covered with a resin &lt;b&gt;13&lt;/b&gt;A. In ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/t7elsooLrdlkO8MqpItqJDGGN3c/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/t7elsooLrdlkO8MqpItqJDGGN3c/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/t7elsooLrdlkO8MqpItqJDGGN3c/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/t7elsooLrdlkO8MqpItqJDGGN3c/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/zl4I7aEM3Ks" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Ceramic multi-layer circuit substrate and manufacturing method thereof]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/3ZkRWhh77lk/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106306&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Kim, Yong Suk; Lee, Taek Jung; Chang, Byeung Gyu; Yoo, Won Hee&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Provided is a method of manufacturing a ceramic multi-layer circuit substrate. A plurality of ceramic blocks, in each of which one or more ceramic green sheets having via-electrodes are layered one atop the other, are formed and are then fired. The fired ceramic blocks are aligned with each other. One or more bonding green sheets each having bonding electrodes in positions corresponding to the via-electrodes of the ceramic blocks are prepared. Each of the bonding green sheets is interposed ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/4lZvBruja4uCie6cBF8HAeckrnw/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/4lZvBruja4uCie6cBF8HAeckrnw/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/4lZvBruja4uCie6cBF8HAeckrnw/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/4lZvBruja4uCie6cBF8HAeckrnw/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/3ZkRWhh77lk" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Print circuit board with high insulated region, method of manufacturing thereof, and print circuit board assembly thereof]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/7buZ4Eyccbg/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106305&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Tokuno, Koji; Goto, Masaharu; Uchida, Minoru&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A print circuit board includes: a first surface; a guard plane disposed on an inner layer; a high insulated region formed on the first surface of the board so as to be opposed to the guard plane, the high insulated region being substantially surrounded by one or more first guard patterns; and a quasi-high insulated region formed on the first surface of the board so as to be disposed adjacent to the high insulated region. The quasi-high insulated region is substantially surrounded by at ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/GVdtELBgno1OI07g3uRfOT9YDvQ/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/GVdtELBgno1OI07g3uRfOT9YDvQ/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/GVdtELBgno1OI07g3uRfOT9YDvQ/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/GVdtELBgno1OI07g3uRfOT9YDvQ/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/7buZ4Eyccbg" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8106305/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Mounting structure of electronic component]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/4-XgclTe9DI/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106304&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Hashimoto, Nobuaki&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A mounting structure of an electronic component includes: a bump electrode included in the electronic component, the bump electrode having an internal resin as a core and a conductive film covering a surface of the internal resin, and elastically deforming so as to follow a shape of at least one corner of a terminal so that the conductive film makes direct conductive contact with at least part of a top surface of the terminal and at least part of a surface along a thickness direction of the ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/fZdNPcXu69YFFbEH31C-dypMzOg/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/fZdNPcXu69YFFbEH31C-dypMzOg/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/fZdNPcXu69YFFbEH31C-dypMzOg/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/fZdNPcXu69YFFbEH31C-dypMzOg/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/4-XgclTe9DI" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8106304/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Printed wiring board including a thermal land for supressing heat dissipation]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/utq2J5EZmwQ/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106303&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Ishida, Hisashi&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;When soldering is performed, heat transferred from through hole &lt;b&gt;6&lt;/b&gt;&lt;i&gt;b &lt;/i&gt;is caused to bypass a mesh-like copper foil region between non-copper-foil regions and thus the transfer of heat to a solid pattern region around thermal land &lt;b&gt;13&lt;/b&gt;&lt;i&gt;b &lt;/i&gt;is delayed. Signal wirings &lt;b&gt;8&lt;/b&gt;&lt;i&gt;e&lt;/i&gt;&lt;b&gt;, 8&lt;/b&gt;&lt;i&gt;f &lt;/i&gt;and signal wirings &lt;b&gt;8&lt;/b&gt;&lt;i&gt;g&lt;/i&gt;&lt;b&gt;, 8&lt;/b&gt; are formed along the arrangement directions of non-copper-foil regions &lt;b&gt;15&lt;/b&gt;&lt;i&gt;b&lt;/i&gt;&lt;b&gt;, 16&lt;/b&gt;&lt;i&gt;b &lt;/i&gt;respectively keeping ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/-9iI-_y6c9KZfwWkD6Drzq3tnf8/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/-9iI-_y6c9KZfwWkD6Drzq3tnf8/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/-9iI-_y6c9KZfwWkD6Drzq3tnf8/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/-9iI-_y6c9KZfwWkD6Drzq3tnf8/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/utq2J5EZmwQ" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8106303/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Circuit board of communication product and manufacturing method thereof]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/bt3vjxuCdmg/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106302&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Hsieh, Ching-Feng; Yu, Jen-Huan; Huang, Chung-Shao; Dai, Cheng-Wen; Chen, Kuo-Ching&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;The present invention provides a circuit board of a communication product and a manufacturing method thereof. The circuit board comprises a main body of a circuit board and an isolation cover. A surface of the main body of the circuit board has a power transistor, an insulating layer, a plurality of first openings disposed at intervals on the insulating layer and around the power transistor, and a plurality of soldering portions exposed from the first openings respectively. The isolation ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/TKvhElYtH4Xprt5DJNL3Nkm3RNw/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/TKvhElYtH4Xprt5DJNL3Nkm3RNw/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/TKvhElYtH4Xprt5DJNL3Nkm3RNw/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/TKvhElYtH4Xprt5DJNL3Nkm3RNw/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/bt3vjxuCdmg" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Connecting member]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/IPrpLDBfSBo/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106301&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Chen, Li-Ping; Hsieh, Chung-Cheng&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A connecting member includes a cable configured to transfer signal, two securing members, and a resilient component. The two securing members secure the resilient component to the cable, the resilient component is elastically deformable between a first state, in which the resilient component and the cable are contracted, and a second state, in which the resilient component and the cable are ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/g3QL9zB5KfXhVyM6tzp2tgSIXRw/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/g3QL9zB5KfXhVyM6tzp2tgSIXRw/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/g3QL9zB5KfXhVyM6tzp2tgSIXRw/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/g3QL9zB5KfXhVyM6tzp2tgSIXRw/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/IPrpLDBfSBo" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8106301/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Split flex cable]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/Ke1MTBGi4D4/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106300&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Clark, Mark G.; Dangler, John R.; Braun, David J.; Stoll, Jason T.; Doyle, Matthew S.; Kidd, Thomas D.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A cable assembly for interconnecting a plurality of circuit boards together by using a connector assembly connected to each of the circuit boards. The cable assembly includes a first cable having a first end part and a second cable having a second end part. A first periphery of the first end part has a plurality of first half vias that collectively form a column along a width direction of the connector assembly. A second periphery of the second end part has a plurality of second half vias ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/C6sudC20XcxFLq-Zb0s0QXi_Oik/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/C6sudC20XcxFLq-Zb0s0QXi_Oik/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/C6sudC20XcxFLq-Zb0s0QXi_Oik/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/C6sudC20XcxFLq-Zb0s0QXi_Oik/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/Ke1MTBGi4D4" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8106300</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8106300/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Multi conductor cable for a portable electric tool]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/Vq7fod1U9Eo/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106299&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Elsmark, Karl Johan Lars&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A multi conductor flat type cable, which is intended for connecting a portable electric power tool to a stationary power supply and operation control unit, has a connector plug (&lt;b&gt;18&lt;/b&gt;) attached to its one end, wherein the cable (&lt;b&gt;10&lt;/b&gt;) has a twisted shape section (A) adjacent the connector plug (&lt;b&gt;18&lt;/b&gt;) for facilitating universal bending of the cable (&lt;b&gt;10&lt;/b&gt;). The twisted section (A) is provided with a transition sleeve (&lt;b&gt;16&lt;/b&gt;) with a cylindrical portion (&lt;b&gt;17&lt;/b&gt;) at the ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/FyZX3-5BQux87lyxZa3Z-Pqkljo/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/FyZX3-5BQux87lyxZa3Z-Pqkljo/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/FyZX3-5BQux87lyxZa3Z-Pqkljo/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/FyZX3-5BQux87lyxZa3Z-Pqkljo/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/Vq7fod1U9Eo" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8106299/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Electrical component comprising a hotmelt element, method and tool for manufacturing such an electrical component]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/smCeUlLcdT4/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106298&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;van Tiel, Gert; Van Tilburg, Jan&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electrical component having at least one cable element, at least one solder joint, at least one hotmelt element and at least one substrate element, a method of manufacturing such an electrical component, and a tool for manufacturing the electrical component. The cable element is connected with the substrate element by the solder joint. The at least one solder joint is not embedded in the hotmelt element. Preferably, the solder joint is free from the hotmelt material of the hotmelt ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/OkwqddMeQZQSpJIKR17tfZL0d1U/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/OkwqddMeQZQSpJIKR17tfZL0d1U/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/OkwqddMeQZQSpJIKR17tfZL0d1U/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/OkwqddMeQZQSpJIKR17tfZL0d1U/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/smCeUlLcdT4" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8106298/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Grounded conduit bushing]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/93JSKjTfutA/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106297&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Kiely, Kenneth M.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;By providing a grounding conductor assembly affixed to a conduit bushing in a manner which enables the grounding conductor assembly to extend inwardly from the bushing, effectively being positioned coaxially with the inside diameter of the rigid metal conduit, conduit bushing is realized which enables all grounding wires to be quickly and easily mounted to the grounding conductor assembly. The conduit bushing of the present invention includes a generally circular shaped cover or cap member ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/_J-foehlwtpGiYVo6o00kWR0gW4/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/_J-foehlwtpGiYVo6o00kWR0gW4/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/_J-foehlwtpGiYVo6o00kWR0gW4/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/_J-foehlwtpGiYVo6o00kWR0gW4/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/93JSKjTfutA" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Electrical component comprising a hotmelt element]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/FNWZPMjJxbE/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106296&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;van Tiel, Gert; Van Tilburg, Jan&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electrical component having at least one cable element, at least one solder joint, at least one hotmelt element and at least one substrate element. The cable element is connected with the substrate element by the solder joint. The at least one solder joint is not embedded in the hotmelt element. Preferably, the solder joint is free from the hotmelt material of the hotmelt ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/dIXAjxmFpHhhAujKYQNAKI3RUbE/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/dIXAjxmFpHhhAujKYQNAKI3RUbE/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/dIXAjxmFpHhhAujKYQNAKI3RUbE/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/dIXAjxmFpHhhAujKYQNAKI3RUbE/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/FNWZPMjJxbE" height="1" width="1"/&gt;</description>
			         
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<item>
			         <title><![CDATA[Apparatus and method for collapsible and expandable electrical device cover]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/K0M1WSnbsoo/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8106295&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Shotey, Marcus J.; Baldwin, Jeffrey P.; Dieterle, Iven&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electrical device cover having a base with a wall structure includes of at least a two pairs of opposing walls located perpendicular to each other and an opening in a back side large enough to receive an electrical device. An exterior surface of at least a first wall has at least one rails running perpendicular to a plane in which the back side of the base resides and the base of a detachable hinge component is slidably coupled to the at least one rail. The detachable hinge component ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/AJ1lcyoPPkck26b3LOcDc63lwk0/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/AJ1lcyoPPkck26b3LOcDc63lwk0/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/AJ1lcyoPPkck26b3LOcDc63lwk0/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/AJ1lcyoPPkck26b3LOcDc63lwk0/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/K0M1WSnbsoo" height="1" width="1"/&gt;</description>
			         
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<item>
			         <title><![CDATA[Watertight junction box]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/tLlCJu1CE2w/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101874&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Yang, Jerry S. C.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A watertight junction box includes a box body, a lower floating plate, an upper floating plate, a lock cap, a modular cable inserted into the box body and kept in contact with sharp copper contacts, a holding down plate for holding down an external power wire on the upper floating plate to cause electric contact between the external power wire and the sharp copper contacts, and a predetermined amount of silicon rubber filled in between the lower and upper floating plate that is deformed to ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/84YceAoyhR2TDEcPDA5nCfg-XUk/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/84YceAoyhR2TDEcPDA5nCfg-XUk/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/84YceAoyhR2TDEcPDA5nCfg-XUk/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/84YceAoyhR2TDEcPDA5nCfg-XUk/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/tLlCJu1CE2w" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Protective structure for a circuit board and method for fabricating the same]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/ZbmvFBff3iM/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101873&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Bungo, Keiichiro&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;In a protective structure for a circuit board (&lt;b&gt;1&lt;/b&gt;) that includes a casing (&lt;b&gt;3&lt;/b&gt;) for receiving the circuit board, the casing is provided with a recess (&lt;b&gt;11&lt;/b&gt;) for receiving a large component part protruding from the circuit board therein, and potting material (&lt;b&gt;6&lt;/b&gt;) is filled in a space defined between the large component part and a surrounding wall of the recess. Typically, the potting material is filled in a gap between the large component part and the surrounding wall ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/qnIgnjeOSws_FeYY-TWUgR1Q7nQ/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/qnIgnjeOSws_FeYY-TWUgR1Q7nQ/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/qnIgnjeOSws_FeYY-TWUgR1Q7nQ/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/qnIgnjeOSws_FeYY-TWUgR1Q7nQ/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/ZbmvFBff3iM" height="1" width="1"/&gt;</description>
			         
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<item>
			         <title><![CDATA[Mobile sound and light resistant electromagnetic isolation chamber]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/i4zPDFUHHc8/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101872&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Malone, William G.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A device enclosing a volume shielded from certain levels of sound, light and electromagnetic radiation, such device that prevents electromagnetic communications and recording devices from transmitting and receiving communications from outside of the devices protected environment while remaining mobile and ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/RBXPb5gDNsxSW1NUUYo8HxHDDTQ/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/RBXPb5gDNsxSW1NUUYo8HxHDDTQ/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/RBXPb5gDNsxSW1NUUYo8HxHDDTQ/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/RBXPb5gDNsxSW1NUUYo8HxHDDTQ/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/i4zPDFUHHc8" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8101872/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Aluminum bond pads with enhanced wire bond stability]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/ZwXJGEwsykw/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101871&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Osenbach, John W.; Baiocchi, Frank A.; DeLucca, John M&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electronic device bond pad includes an Al layer located over an electronic device substrate. The Al layer includes an intrinsic group 10 metal located ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/ujF0OlCkIqvjvN-G_gCiYL_Rzmc/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/ujF0OlCkIqvjvN-G_gCiYL_Rzmc/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/ujF0OlCkIqvjvN-G_gCiYL_Rzmc/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/ujF0OlCkIqvjvN-G_gCiYL_Rzmc/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/ZwXJGEwsykw" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Method for manufacturing printed circuit board, printed circuit board, and electronic apparatus]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/NlF6du_AmSA/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101870&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Ishii, Norihiro&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A method for manufacturing a printed circuit board. The method includes: preparing a printed wiring board, the printed wiring board comprising through holes and a plurality of electrode pads; coating surfaces of the plurality of electrode pads and surfaces of the through holes on an one side of the printed wiring board with a bonding material; mounting a semiconductor package on the printed wiring board such that a plurality of bumps on a surface of the semiconductor package corresponds to ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/diZov-rqy2KuaMOGbU9xjqdw2Xs/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/diZov-rqy2KuaMOGbU9xjqdw2Xs/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/diZov-rqy2KuaMOGbU9xjqdw2Xs/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/diZov-rqy2KuaMOGbU9xjqdw2Xs/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/NlF6du_AmSA" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Mounting structure, electro-optical device, and electronic apparatus]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/FDcy5WL2UoY/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101869&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Kurasawa, Munenori&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A mounting structure includes a member to be bonded, a flexible base, a reinforcing portion, and a bonding member. The flexible base includes a plurality of first leads. The reinforcing portion is arranged between an edge of the flexible base and an outer lead of the plurality of first leads and has a width larger than that of the outer lead. The bonding member bonds the member to be bonded and the flexible base ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/oFLwt2WysaN2vUy8q9bC7FGKYBM/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/oFLwt2WysaN2vUy8q9bC7FGKYBM/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/oFLwt2WysaN2vUy8q9bC7FGKYBM/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/oFLwt2WysaN2vUy8q9bC7FGKYBM/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/FDcy5WL2UoY" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Multilayered printed circuit board and method for manufacturing the same]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/EdrjXUEFe-I/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101868&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Ito, Sotaro; Takahashi, Michimasa; Mikado, Yukinobu&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/bamzzpEEj57LGLeWBYlA70z30WU/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/bamzzpEEj57LGLeWBYlA70z30WU/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/bamzzpEEj57LGLeWBYlA70z30WU/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/bamzzpEEj57LGLeWBYlA70z30WU/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/EdrjXUEFe-I" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Electroless Ni-P plating method and substrate for electronic component]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/Tt4bP19WZfw/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101867&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Yokota, Masayuki; Asada, Ken; Kikui, Fumiaki&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electroless Ni—P plating method according to the present invention includes the steps of: providing a substrate including an insulating substrate and a copper alloy layer that has a predetermined pattern including a plurality of island portions that are isolated from each other; providing a plating solution to carry out electroless Ni—P plating; providing a solid piece including Ni, Ni—P, Co or Co—Ni on at least the surface thereof; and bringing the solid piece into contact with ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/vdlBOpxZSdTtlPZ0lzfwuvomQOU/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/vdlBOpxZSdTtlPZ0lzfwuvomQOU/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/vdlBOpxZSdTtlPZ0lzfwuvomQOU/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/vdlBOpxZSdTtlPZ0lzfwuvomQOU/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/Tt4bP19WZfw" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Packaging substrate with conductive structure]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/RCavySwYyYA/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101866&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Hsu, Shih-Ping&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump ...&lt;br /&gt;
&lt;p&gt;&lt;a href="http://feedads.g.doubleclick.net/~a/kCmBCdGWJphBdWp05mWOzdzomM8/0/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/kCmBCdGWJphBdWp05mWOzdzomM8/0/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;br/&gt;
&lt;a href="http://feedads.g.doubleclick.net/~a/kCmBCdGWJphBdWp05mWOzdzomM8/1/da"&gt;&lt;img src="http://feedads.g.doubleclick.net/~a/kCmBCdGWJphBdWp05mWOzdzomM8/1/di" border="0" ismap="true"&gt;&lt;/img&gt;&lt;/a&gt;&lt;/p&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~4/RCavySwYyYA" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Printed wiring board and a method of production thereof]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/fdqfBoG8im4/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101865&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;Ikeda, Tomoyuki&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A printed wiring board has an insulating resin substrate having a first surface and a second surface, the insulating resin substrate having one or more penetrating-holes passing through the insulating resin substrate from the first surface to the second surface, a first conductor formed on the first surface of the insulating resin substrate, a second conductor formed on the second surface of the insulating resin substrate, and a through-hole conductor structure formed in the ...&lt;br /&gt;
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8101865/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Electronic device substrate and its fabrication method, and electronic device and its fabrication method]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/pOooJqK-mx0/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101864&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Uchida, Kenji; Hirasawa, Koki; Mita, Mamoru; Chinda, Akira; Miyamoto, Nobuaki&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electronic device substrate is provided with a thin-plate core substrate; a metal electrode provided on the core substrate and electrically connected to an electrode of an electronic component to be packaged thereon; and an electrical insulation layer on which is mounted the electronic component, and which is provided to surround the metal ...&lt;br /&gt;
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8101864/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Printed circuit board]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/lUgGN4JPXs8/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101863&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Honjo, Mitsuru; Yamazaki, Natsuko&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A plurality of wiring patterns are formed on a first surface of a base insulating layer, and a ground layer is formed on a second surface opposite to the first surface. A cover insulating layer is then formed on the first surface of the base insulating layer so as to cover the plurality of wiring patterns. Further, a cover insulating layer is formed on the second surface of the base insulating layer so as to cover the ground layer. A high dielectric insulating layer having a dielectric ...&lt;br /&gt;
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			         <title><![CDATA[Self-sealing electrical cable using rubber resins]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/kY6m061FK2g/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101862&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Sasse, Philip Anthony; Reece, David; Spruell, Stephen Lee; Nuckles, Kimberly M.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electrical cable and a method for manufacturing the electrical cable are provided in which a plurality of insulated conductors have an inner protective layer extruded thereabout. A plurality of longitudinally extending ribs or fins or exterior ribbed or finned surfaces are formed outward of the inner protective layer between which exist a plurality of voids. An outer insulation layer can be formed in the same operation as the fins or ribbed surface and the inner layer or in a subsequent ...&lt;br /&gt;
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			         <title><![CDATA[Electrical device cover]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/VnK5qymCP1M/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101861&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Cleghorn, Richard; Shotey, Marcus J.; Baldwin, Jeffrey P.; Booth, Kenneth C.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A cover for electrical devices is disclosed. Particular implementations include an electrical device cover configured to mount over an electrical device includes a lid having a flexible membrane. The lid is coupled by a hinge to a base and the cover includes a cord port in an edge of a surface of the cover. The lid is configured to expand through the flexible membrane to an expanded position to accommodate an electrical connector coupled with the electrical device. The lid may also be ...&lt;br /&gt;
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			         <title><![CDATA[Electrical device cover]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-ElectricityConductorsAndInsulators/~3/eXtkm-DZcPc/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8101860&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Cleghorn, Richard L.; Maltby, Edgar W.; Baca, Andre; Shotey, Marcus J.; Baldwin, Jeffrey P.; Booth, Kenneth C.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electrical device cover configured for mounting over an electrical device comprises a frame including a frame channel and an frame opening. The frame opening is defined by at least four sides and is large enough to receive at least one electrical device. A sliding tab comprising a screw channel is provided, the sliding tab is slidably coupled with the frame channel and is slideable to a closed position in which the screw channel at least partially surrounds a box mounting screw of the at ...&lt;br /&gt;
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