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		    <title>PatentStorm -&gt; Patents -&gt; Electrical pulse counters, pulse dividers, or shift registers: circuits and systems</title>
		    <link>http://www.patentstorm.us/rss/class/patents/rss-377.xml</link>
		    <description>Recent patents filings in USPTO Class 377 Electrical pulse counters, pulse dividers, or shift registers: circuits and systems.</description>
		    <pubDate>Tue, 7 Feb 2012 16:05:18</pubDate>
		    <managingEditor>patents@patentstorm.us</managingEditor>
		    <language>en</language><atom10:link xmlns:atom10="http://www.w3.org/2005/Atom" rel="self" type="application/rss+xml" href="http://feeds.feedburner.com/Patentstorm-Patents-ElectricalPulseCountersPulseDividersOrShiftRegistersCircuitsAndSystems" /><feedburner:info xmlns:feedburner="http://rssnamespace.org/feedburner/ext/1.0" uri="patentstorm-patents-electricalpulsecounterspulsedividersorshiftregisterscircuitsandsystems" /><atom10:link xmlns:atom10="http://www.w3.org/2005/Atom" rel="hub" href="http://pubsubhubbub.appspot.com/" /><item>
			         <title><![CDATA[Digital logic circuit, shift register and active matrix device]]></title>
			         <link>http://www.patentstorm.us/patents/8107587/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8107587&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Rajendra, Jaganath; Zebedee, Patrick&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power supply line, respectively. A second transistor has a source, gate and drain connected to the second node, the first node and the first supply line, respectively. A third transistor has a drain connected to the first node. A fourth transistor has a gate and ...&lt;br /&gt;
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			         <title><![CDATA[Shift register and display device including the same]]></title>
			         <link>http://www.patentstorm.us/patents/8107586/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8107586&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-31&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Chae, Chong-Chul; Hong, Mun-Pyo; Roh, Nam-Seok; Shin, Kyong-Ju; Park, Cheol-Woo&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A shift register comprises stages connected to each other, in which each stage generates an output signal in response to any one of clock signals and an output from each of two different stages. Each clock signal has a duty ratio of less than 50% and a different phase from each of the other clock signals. A display device includes pixels, signal lines, and first and second shift registers each having stages connected to each other and generating output signals to signal lines. Each stage ...&lt;br /&gt;
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			         <title><![CDATA[Bidrectional shifter register and method of driving same]]></title>
			         <link>http://www.patentstorm.us/patents/8102962/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8102962&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-24&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Wang, Tsang-Hong; Liu, Sheng-Chao; Liu, Kuang-Hsiang; Tseng, Chien-Chang&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A bidirectional shift register includes first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi&lt;b&gt;1&lt;/b&gt;, Bi&lt;b&gt;2&lt;/b&gt;, Bi&lt;b&gt;3&lt;/b&gt; and Bi&lt;b&gt;4&lt;/b&gt;, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node and a second input node, where the plurality of shift register stages is grouped into a first section and a second section, wherein the first and ...&lt;br /&gt;
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			         <title><![CDATA[Shift register circuit]]></title>
			         <link>http://www.patentstorm.us/patents/8098792/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8098792&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-17&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Chen, Yung-Chih; Liu, Chun-Hsin; Hsu, Kuo-Hua; Lin, Chih-Ying&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is ...&lt;br /&gt;
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			         <title><![CDATA[Shift register]]></title>
			         <link>http://www.patentstorm.us/patents/8098791/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8098791&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2012-01-17&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;Lin, Shih-Chyn; Fan, Hsiang-Pin; Chen, Wen-Pin; Tseng, Kuei-Sheng; Wu, Chen-Yi&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A shift register includes a control circuit, a pull-up circuit and a pull-down circuit. The control circuit generates a control signal according to a start pulse signal during being enabled. The pull-up circuit produces a gate pulse signal according to a clock signal during being enabled by the control signal. The pull-up circuit includes a dual-gate transistor. A first gate of the dual-gate transistor is electrically coupled to the control signal, a second gate of the dual-gate transistor ...&lt;br /&gt;
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