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Gathering and scattering multiple data elements

Patent Number: 8447962
Publication Date: 2013-05-21
Inventors: ; ; ; ; ; ; ; ; ; ;

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or ...

Mechanism for efficient implementation of software pipelined loops in VLIW processors

Patent Number: 8447961
Publication Date: 2013-05-21
Inventors: ; ; ;

A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction buffer size. A program memory receives a Program Memory address to fetch an instruction packet. The program memory is closely coupled with the instruction buffer size to implement the zero overhead software pipelined (SFP) ...

Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition

Patent Number: 8447960
Publication Date: 2013-05-21
Inventors: ; ;

A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor ...

Multithread processor and method of controlling multithread processor

Patent Number: 8447959
Publication Date: 2013-05-21
Inventor:

A plurality of register windows in a multithread processor are each provided for a corresponding thread and capable of storing data to be used for instruction processing in an arithmetic unit. A work register in the multithread processor is capable of mutually transferring data with respect to the register windows and the arithmetic unit. A multithread control unit in the multithread processor controls data transfer among the register windows, the work register and the arithmetic unit on ...

Substituting portion of template instruction parameter with selected virtual instruction parameter

Patent Number: 8447958
Publication Date: 2013-05-21
Inventor:

A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction ...

Coprocessor interface architecture and methods of operating the same

Patent Number: 8447957
Publication Date: 2013-05-21
Inventors: ; ;

A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a multi-channel memory controller, and at least one coprocessor. The processor circuit is coupled to the bus, the multi-channel memory controller is coupled between the bus and the memory circuit, and the coprocessors are coupled to both the processor circuit and the multi-channel memory controller. ...

Running subtract and running divide instructions for processing vectors

Patent Number: 8447956
Publication Date: 2013-05-21
Inventors: ;

The described embodiments provide a processor for generating a result vector with subtracted or mathematically divided values from a first input vector. During operation, the processor receives the first input vector, a second input vector, and a control vector, and optionally receives a predicate vector. The processor then records a value from an element at a key element position in the second input vector into a base value. Next, the processor generates a result vector. When generating ...

Efficient memory update process for well behaved applications executing on a weakly-ordered processor

Patent Number: 8447955
Publication Date: 2013-05-21
Inventor:

A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), which provides an algorithm and a table of lock addresses, within which each lock address is ...

Parallel pipelined vector reduction in a data processing system

Patent Number: 8447954
Publication Date: 2013-05-21
Inventor:

A parallel processing data processing system builds at least one data structure indicating a communication schedule for a plurality of processes each having a respective one of a plurality of equal length vectors formed of multiple equal size chunks. The data processing system, based upon the at least one data structure, communicates chunks of the plurality of vectors among the plurality of processes and performs partial reduction operations on chunks in accordance with the communication ...

Instruction controller to distribute serial and SIMD instructions to serial and SIMD processors

Patent Number: 8447953
Publication Date: 2013-05-21
Inventor:

A microprocessor architecture comprises a plurality of processing elements arranged in a single instruction multiple data SIMD array, wherein each processing element includes a plurality of execution units, each of which is operable to process an instruction of a particular instruction type, a serial processor which includes a plurality of execution units, each of which is operable to process an instruction of a particular instruction type, and an instruction controller operable to receive ...

Bad branch prediction detection, marking, and accumulation for faster instruction stream processing

Patent Number: 8443177
Publication Date: 2013-05-14
Inventor:

An apparatus for extracting instructions from a stream of undifferentiated instruction bytes in a microprocessor having an instruction set architecture in which the instructions are variable length. Decode logic decodes the instruction bytes of the stream to generate for each a corresponding opcode byte indictor and end byte indicator and receives a corresponding taken indicator for each of the instruction bytes. The taken indicator is true if a branch predictor predicted the instruction ...

Method, system, and computer program product for reducing cache memory pollution

Patent Number: 8443176
Publication Date: 2013-05-14
Inventors: ; ;

A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the cache line based on the next predicted taken branch instruction, continuing preventing the fetching for the instruction stream from the sequential cache line if the ...

Microprocessor with first processor for debugging second processor

Patent Number: 8443175
Publication Date: 2013-05-14
Inventor:

A microprocessor integrated circuit includes first and second processors, an internal memory accessible by the first and second processors, and a bus interface unit configured to interface to a bus external to the microprocessor for providing access to a memory external to the microprocessor. The bus interface unit, external bus, and external memory are accessible by the second processor but are inaccessible by the first processor. The first processor writes debug information to the ...

Processor and method of performing speculative load operations of the processor

Patent Number: 8443174
Publication Date: 2013-05-14
Inventors: ;

Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a ...

Method for instructing a data processor to process data

Patent Number: 8443173
Publication Date: 2013-05-14
Inventor:

A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as ...

Apparatus and method for marking start and end bytes of instructions in a stream of instruction bytes in a microprocessor having an instruction set architecture in which instructions may include a length-modifying prefix

Patent Number: 8443172
Publication Date: 2013-05-14
Inventor:

An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying ...

Run-time updating of prediction hint instructions

Patent Number: 8443171
Publication Date: 2013-05-14
Inventors: ;

The present invention provides a system and method for runtime updating of hints in program instructions. The invention also provides for programs of instructions that include hint performance data. Also, the invention provides an instruction cache that modifies hints and writes them back. As runtime hint updates are stored in instructions, the impact of the updates is not limited by the limited memory capacity local to a processor. Also, there is no conflict between hardware and software ...

Apparatus and method for performing SIMD multiply-accumulate operations

Patent Number: 8443170
Publication Date: 2013-05-14
Inventors: ;

An apparatus and method for performing SIMD multiply-accumulate operations includes SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements. Instruction decoder circuitry is coupled to the SIMD data processing circuitry and is responsive to program instructions to generate the required control signals. The instruction decoder circuitry is responsive to a single instruction (referred to herein as a repeating ...

Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor

Patent Number: 8443169
Publication Date: 2013-05-14
Inventor:

A Wings array system for communicating between nodes using store and load instructions is described. Couplings between nodes are made according to a 1 to N adjacency of connections in each dimension of a G×H matrix of nodes, where G≧N and H≧N and N is a positive odd integer. Also, a 3D Wings neural network processor is described as a 3D G×H×K network of neurons, each neuron with an N×N×N array of synaptic weight values stored in coupled memory nodes, where G≧N, H≧N, K≧N, and ...

Method and system for implementing efficient locking to facilitate parallel processing of IC designs

Patent Number: 8438512
Publication Date: 2013-05-07
Inventors: ;

Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize ...

Link stack repair of erroneous speculative update

Patent Number: 8438372
Publication Date: 2013-05-07
Inventors: ;

Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining an incrementing tag register which is incremented by each link stack write instruction entering the pipeline, and a snapshot of the incrementing tag register, associated with each branch instruction. When a branch is ...

Link stack repair of erroneous speculative update

Patent Number: 8438371
Publication Date: 2013-05-07
Inventors: ;

Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated ...

Processing of loops with internal data dependencies using a parallel processor

Patent Number: 8438370
Publication Date: 2013-05-07
Inventor:

Loops with internal data dependencies (e.g., in a Mersenne Twister pseudorandom number generator) are implemented by exploiting arrays of cooperating threads that can be executed concurrently using a suitably configured processor. In one implementation, each thread is assigned to update a different element of a data array where updating of later elements depends on updates to earlier elements. Thread synchronization techniques are advantageously used to control the order in which different ...

Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor

Patent Number: 8438369
Publication Date: 2013-05-07
Inventors: ; ;

A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the ...

Processing apparatus, processing system, and computer readable medium

Patent Number: 8438368
Publication Date: 2013-05-07
Inventor:

Optimizing processing of a document sequentially processed by a plurality of image processing apparatuses that refer to an instruction document indicating the processing to be performed by each of the plurality of image processing apparatuses and respective security measures performed by each of the plurality of image processing ...

Instruction extraction through prefix accumulation

Patent Number: 8438367
Publication Date: 2013-05-07
Inventor:

An apparatus has a queue, each entry stores a different line of a stream of instruction bytes and accumulated prefix information associated with each instruction byte. Control logic: (a) detects a condition where an initial portion of an instruction partially within a first line stored in the bottom entry (BE) of the queue remains unextracted from the queue, wherein the initial portion instruction bytes are all prefix bytes; (b) saves away the initial portion length, shifts the first line ...

Allocating rename register from separate register sets for each result data of multiple data processing instruction

Patent Number: 8438366
Publication Date: 2013-05-07
Inventor:

Multiple data processing instructions instruct a computing device to process multiple data including first data and second data. When a multiple data processing instruction is decoded, two allocatable registers are selected. One is used to store the result of a processing operation performed on first data by one processing unit, and the other is used to store the result of a processing operation performed on second data by another processing unit. Those stored processing results are then ...

Method, system and computer-accessible medium for providing a distributed predicate prediction

Patent Number: 8433885
Publication Date: 2013-04-30
Inventor:

Examples of a system, method and computer accessible medium are provided to generate a predicate prediction for a distributed multi-core architecture. Using such system, method and computer accessible medium, it is possible to intelligently encode approximate predicate path information on branch instructions. Using this statically generated information, distributed predicate predictors can generate dynamic predicate histories that can facilitate an accurate prediction of high-confidence ...

Multiprocessor

Patent Number: 8433884
Publication Date: 2013-04-30
Inventor:

A multiprocessor executes a plurality of threads without decreasing execution efficiency. The multiprocessor includes a first processor allocating a different register file to each of a predetermined number of threads to be executed from among plural threads, and executing the predetermined number of threads in parallel; and a second processor performing processing according to a processing request made by the first processor. The first processor has areas allocated to the plurality of ...

Inclusive “OR” bit matrix compare resolution of vector update conflict masks

Patent Number: 8433883
Publication Date: 2013-04-30
Inventors: ; ; ;

A computer system is operable to identify index elements in a vector index array that cannot be processed in parallel by calculating a complement modified bit matrix compare function between a first matrix filled with elements from the vector index array and a second matrix filled with the same elements from the vector index ...