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Method of Manufacturing Semiconductor Device, Method of Processing Substrate, Substrate Processing Apparatus and Non-Transitory Computer-Readable Recording Medium

Application Number: 20130149874
Publication Date: 2013-06-13
Inventor: HITACHI KOKUSAI ELECTRIC INC.,

A method of manufacturing a semiconductor device is provided. The method includes: forming a thin film containing a predetermined element on a substrate by repeating a cycle, the cycle including: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and a halogen element to the substrate and supplying a first reactive gas containing three elements including the carbon, the nitrogen ...

Method of Manufacturing Semiconductor Device, Method of Processing Substrate, Substrate Processing Apparatus and Non-Transitory Computer-Readable Recording Medium

Application Number: 20130149873
Publication Date: 2013-06-13
Inventor: HITACHI KOKUSAI ELECTRIC INC.,

A thin film including characteristics of low permittivity, high etching resistance and high leak resistance is to be formed. A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element on a substrate by performing a cycle a predetermined number of times, the cycle including: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM

Application Number: 20130149872
Publication Date: 2013-06-13
Inventors: L'AIR LIQUIDE-SOCIETE ANONYME POUR L'ET, ; HITACHI KOKUSAI ELECTRIC INC.,

There is provided a method of manufacturing a semiconductor device, including: forming a film containing a specific element, nitrogen, and carbon on a substrate, by alternately performing the following steps a specific number of times: a step of supplying a source gas containing the specific element and a halogen element, to the substrate; and a step of supplying a reactive gas composed of three elements of carbon, nitrogen, and hydrogen and having more number of a carbon atom than the number ...

CHEMICAL VAPOR DEPOSITION FILM PROFILE UNIFORMITY CONTROL

Application Number: 20130149871
Publication Date: 2013-06-13
Inventors: Lee, Chih-Tsung; Tsai, Ming-Chin; Lin, Chin-Hsiang; Chou, You-Hua; Chen, Chia-Ho; Kuo, Ming-Shiou

The present disclosure provides for methods and systems for controlling profile uniformity of a chemical vapor deposition (CVD) film. A method includes depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile, and depositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile. The combined first layer and second layer have a third profile, and the first profile, the second profile, ...

SUBSTRATE CARRIER AND APPLICATIONS THEREOF

Application Number: 20130149870
Publication Date: 2013-06-13
Inventors: Tung, Chun-Hsing; Lin, Fei-Tzu

A substrate carrier for performing a deposition process comprises a supporting element and a cover element. The supporting element having a through hole is used to carry a substrate. The cover element is removably engaged with the supporting element, so as to secure the substrate therebetween and expose a deposition surface of the substrate from the through ...

SILICON ON INSULATOR ETCH

Application Number: 20130149869
Publication Date: 2013-06-13
Inventors: HEFTY, Robert C.; ROBSON, Mark Todhunter; BOWERS, James R.; CHARLES, Audrey; LI, Siyi

A method etching features through a stack of a silicon nitride layer over a silicon layer over a silicon oxide layer in a plasma processing chamber is provided. The silicon nitride layer is etched in the plasma processing chamber, comprising; flowing a silicon nitride etch gas; forming the silicon nitride etch gas into a plasma to etch the silicon nitride layer, and stopping the flow of the silicon nitride etch gas. The silicon layer is, comprising flowing a silicon etch gas, wherein the ...

Masking Method and Apparatus

Application Number: 20130149868
Publication Date: 2013-06-13
Inventor: Satitpunwaycha, Peter

A chamber for combinatorially processing a substrate is provided. The chamber includes a first mask and a second mask that share a common central axis. The first mask and the second mask are independently rotatable around the common central axis. The first mask has a first plurality of radial apertures and the second mask has a second plurality of radial apertures. An axis of the first plurality of radial apertures is offset from an axis of the second plurality of radial apertures. A substrate ...

SUBSTRATE PROCESSING SYSTEM, GAS SUPPLY UNIT, METHOD OF SUBSTRATE PROCESSING, COMPUTER PROGRAM, AND STORAGE MEDIUM

Application Number: 20130149867
Publication Date: 2013-06-13
Inventor: Tokyo Electron Limited,

The present invention is to provide a technique for uniformly processing a substrate surface in the process of processing a substrate by supplying a gas. The inside of a shower head having gas-jetting pores for supplying a gas to a substrate is partitioned into a center section from which a gas is supplied to the center portion of a substrate, and a peripheral section from which a gas is supplied to the peripheral portion of the substrate, and the same process gas is supplied to the substrate ...

BAFFLE PLATE FOR SEMICONDUCTOR PROCESSING APPARATUS

Application Number: 20130149866
Publication Date: 2013-06-13
Inventor: SHRINER, JOHN CHRISTOPHER

A baffle plate for redirecting a reactive gas flow within a process chamber of a semiconductor plasma processing apparatus includes a topside surface having a plurality of topside apertures for receiving the reactive gas flow and a bottomside surface having a plurality of bottomside apertures for emitting the reactive gas flow toward a semiconductor substrate. An outer portion of the baffle plate includes both topside apertures and bottomside apertures, while within an inner portion of the ...

METHOD AND STRUCTURE FOR DIFFERENTIAL SILICIDE AND RECESSED OR RAISED SOURCE/DRAIN TO IMPROVE FIELD EFFECT TRANSISTOR

Application Number: 20130149865
Publication Date: 2013-06-13
Inventor: International Business Machines Corporation,

A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type ...

Semiconductor Device and Manufacturing Method Thereof

Application Number: 20130149864
Publication Date: 2013-06-13
Inventor: Hitachi, Ltd.,

Wirings mainly containing copper are formed on an insulating film on a substrate. Then, after forming insulating films for reservoir pattern and a barrier insulating film, an insulating film for suppressing or preventing diffusion of copper is formed on upper and side surfaces of the wirings, the insulating film on the substrate, and the barrier insulating film. Here, thickness of the insulating film for suppressing or preventing diffusion of copper at the bottom of a narrow inter-wiring space ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE BY DAMASCENE PROCESS

Application Number: 20130149863
Publication Date: 2013-06-13
Inventor: YU, Jae-Seon

A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the ...

METHOD FOR FORMING FINE PATTERN HAVING VARIABLE WIDTH AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

Application Number: 20130149862
Publication Date: 2013-06-13
Inventor: Samsung Electronics Co., Ltd.,

A method for forming a fine pattern having a variable width by simultaneously using an optimal focused electron beam and a defocused electron beam in a light exposure process Includes, after forming a first film on a substrate, forming a first film pattern including a first level area and a second level area having different distances from the substrate by changing a profile of an upper surface of the first film. A photoresist film having a first area covering the first level area and a second ...

CONTACT FOR MEMORY CELL

Application Number: 20130149861
Publication Date: 2013-06-13
Inventor: MICRON TECHNOLOGY, INC.,

A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such ...

Metal Silicide Nanowire Arrays for Anti-Reflective Electrodes in Photovoltaics

Application Number: 20130149860
Publication Date: 2013-06-13
Inventors: Honda Motor Company., LTD, ; Junior University, The Board of Trustees of the Leland Stanford

A method of fabricating single-crystalline metal silicide nanowires for anti-reflective electrodes for photovoltaics is provided that includes exposing a surface of a metal foil to oxygen or hydrogen at an elevated temperature, and growing metal silicide nanowires on the metal foil surface by flowing a silane gas mixture over the metal foil surface at the elevated temperature, where spontaneous growth of the metal silicide nanowires occur on the metal foil surface, where the metal silicide ...

TUNGSTEN METALLIZATION: STRUCTURE AND FABRICATION OF SAME

Application Number: 20130149859
Publication Date: 2013-06-13
Inventor: International Business Machines Corporation,

A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first ...

METHOD OF MANUFACTURING BUMP

Application Number: 20130149858
Publication Date: 2013-06-13
Inventor: Samsung Electronics Co., Ltd.,

A bump manufacturing method may be provided. The bump manufacturing method may include forming a bump on an electrode pad included in a semiconductor device, and controlling a shape of the bump by reflowing the bump formed on the semiconductor device under an oxygen ...

SOLDER INTERCONNECT BY ADDITION OF COPPER

Application Number: 20130149857
Publication Date: 2013-06-13
Inventor: LSI Corporation,

A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow ...

Interface Structure for Copper-Copper Peeling Integrity

Application Number: 20130149856
Publication Date: 2013-06-13
Inventor: Semiconductor Manufacturing Company, Ltd., Taiwan

An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Application Number: 20130149855
Publication Date: 2013-06-13
Inventor: Renesas Electronics Corporation,

To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Application Number: 20130149854
Publication Date: 2013-06-13
Inventor: RENESAS ELECTRONICS CORPORATION,

An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Application Number: 20130149853
Publication Date: 2013-06-13
Inventor: Sumitomo Electric Industries, Ltd.,

A method for manufacturing a semiconductor device includes the steps of: preparing a substrate; forming a gate insulating film; forming a gate electrode; forming an interlayer insulating film to surround the gate electrode; forming a contact hole extending through the interlayer insulating film to expose a main surface of the substrate; and forming a first metal film on and in contact with a side wall surface of the contact hole, the first metal film containing at least one of Ti and Si and ...

METHOD FOR FORMING A SEMICONDUCTOR DEVICE

Application Number: 20130149852
Publication Date: 2013-06-13
Inventors: Nakamura, Genji; Hasegawa, Toshio

A method for forming a semiconductor device includes providing in a process chamber a metal-containing gate electrode film on a substrate, flowing a process gas consisting of hydrogen (H₂) and optionally a noble gas into the process chamber, forming plasma excited species from the process gas by a microwave plasma source, and exposing the metal-containing gate electrode film to the plasma excited species to form a modified metal-containing gate electrode film having a lower work ...

Methods of Protecting Elevated Polysilicon Structures During Etching Processes

Application Number: 20130149851
Publication Date: 2013-06-13
Inventors: Li, Liang; Rao, Xue Song; Zhou, Peng; See, Alex; Siah, Soh Yun; Liu, Huang

Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Application Number: 20130149850
Publication Date: 2013-06-13
Inventor: Sumitomo Electric Industries, Ltd.,

A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main ...

COMBINING ZTCR RESISTOR WITH LASER ANNEAL FOR HIGH PERFORMANCE PMOS TRANSISTOR

Application Number: 20130149849
Publication Date: 2013-06-13
Inventor: TEXAS INSTRUMENTS INCORPORATED,

An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond ...

METHOD FOR MANUFACTURING VERTICAL-CHANNEL TUNNELING TRANSISTOR

Application Number: 20130149848
Publication Date: 2013-06-13
Inventors: WANG, PENGFEI; LIN, XI; LIU, WEI; SUN, QINGQING; ZHANG, WEI

The present invention belongs to the technical field of semiconductors and specifically relates to a method for manufacturing a vertical-channel tunneling transistor. In the present invention, the surrounding gate gate structure improves the control capacity of the gate and the source of narrow band gap material can enhance the device driving current. The method for manufacturing a vertical-channel tunneling transistor put forward by the present invention capable of controlling the channel ...

METHOD OF MANUFACTURING GaN-BASED FILM AND COMPOSITE SUBSTRATE USED THEREFOR

Application Number: 20130149847
Publication Date: 2013-06-13
Inventors: Satoh, Issei; Uematsu, Koji; Yoshimura, Masashi; Yamamoto, Yoshiyuki; Fujiwara, Shinsuke; Seki, Yuki; Matsubara, Hideki

The present method of manufacturing a GaN-based film includes the steps of preparing a composite substrate including a support substrate dissoluble in hydrofluoric acid and a single crystal film arranged on a side of a main surface of the support substrate, a coefficient of thermal expansion in the main surface of the support substrate being more than 0.8 time and less than 1.2 times as high as a coefficient of thermal expansion of GaN crystal, forming a GaN-based film on a main surface of the ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS

Application Number: 20130149846
Publication Date: 2013-06-13
Inventor: Hitachi Kokusai Electric Inc.,

A film is formed on a substrate by performing a cycle at least twice, the cycle including a nucleus formation process for forming nuclei on the substrate and a nucleus growth suppression process for suppressing growth of the nuclei. A time required for the nucleus growth suppression process is less than or equal to a time required for the nucleus formation process. Alternatively, the nucleus formation process is further performed after the cycle is repeatedly performed a plurality of ...

n- and p-Channel Field Effect Transistors with Single Quantum Well for Complementary Circuits

Application Number: 20130149845
Publication Date: 2013-06-13
Inventors: Bennett, Brian R.; Ancona, Mario; Champlain, James G.; Papanicolaou, Nicolas A.; Boos, John Bradley

A complementary metal oxide semiconductor (CMOS) device in which a single In_xGa_1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The In_xGa_1-xSb layer is part of a heterostructure that includes a Te-delta doped Al_yGa_1-ySb layer above the In_xGa_1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped ...

METHOD OF GROWING ZINC OXIDE NANOWIRE

Application Number: 20130149844
Publication Date: 2013-06-13
Inventors: Baek, Nam Seob; Jung, Sang Don; Kim, Yong Hee

Methods of growing a zinc oxide nanowire are provided. According to the method, developing a photoresist layer and etching a zinc oxide seed layer may be successively performed using a tetramethyl ammonium hydroxide aqueous solution. Thus, change of solutions may not be required, such that the number of processes may be ...

In-situ Gettering Method for Removing Metal Impurities from the Surface and Interior of a Upgraded Metallurgical Grade Silicon Wafer

Application Number: 20130149843
Publication Date: 2013-06-13
Inventors: Jheng, Jin-Jang; Chiang, Chin-Chen; Yang, Tsun-Neng

An in-situ gettering method for removing impurities from the surface and interior of a upgraded metallurgical grade silicon wafer is continuously conducted in a reaction chamber. Chloride gas is mixed with carrier gas. The gaseous mixture is used to clean the surface of the silicon wafer. Then, the gaseous mixture is used to form a porous structure on the surface of the silicon wafer before hot annealing is executed. Finally, the gaseous mixture is used to execute hot etching on the surface of ...

LAMINATED SHEET AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE LAMINATED SHEET

Application Number: 20130149842
Publication Date: 2013-06-13
Inventor: NITTO DENKO CORPORATION,

The present invention provides a laminated sheet that can prevent the decrease in adhering strength of a resin composition layer and the deterioration in electrical reliability and in which a back grinding tape can be peeled from a plurality of semiconductor elements collectively after dicing. The laminated sheet has a back grinding tape in which a pressure-sensitive adhesive layer is formed on a base, and a resin composition layer that is provided on the pressure-sensitive adhesive layer of ...

WAFER DICING EMPLOYING EDGE REGION UNDERFILL REMOVAL

Application Number: 20130149841
Publication Date: 2013-06-13
Inventors: Katsurayama, Satoru; Oka, Daisuke; Okada, Shigefumi; Indyk, Richard F.; Nah, Jae-Woong

In one embodiment, a dielectric material layer embedding metal structures is ablated from the chip-containing substrate by laser grooving, which is performed on dicing channels of the chip-containing substrate. Subsequently, an underfill layer is formed over the dielectric material layer in a pattern that excludes the peripheral areas of the chip-containing substrate. The physically exposed dicing channels at the periphery can be employed to align a blade to dice the chip-containing substrate. ...

METHOD FOR MANUFACTURING SOI SUBSTRATE AND SEMICONDUCTOR DEVICE

Application Number: 20130149840
Publication Date: 2013-06-13
Inventor: ENERGY LABORATORY CO., LTD., SEMICONDUCTOR

It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible ...

APPARATUS FOR BONDING SUBSTRATES TO EACH OTHER

Application Number: 20130149839
Publication Date: 2013-06-13
Inventors: NG, Man Chung; CHAN, Wai Lik; WONG, Kwok Kei

An apparatus for bonding at least two substrates to each other comprises a plurality of substrate bonding machines arranged adjacent to one another and an input transporter extending adjacent to the plurality of substrate bonding machines which is operative to deliver the substrates to each of the substrate bonding machines. The input transporter is supplied with substrates by an onloading station. An output transporter extending adjacent to the plurality of substrate bonding machines is ...

PROCESS FOR FILLING DEEP TRENCHES IN A SEMICONDUCTOR MATERIAL BODY, AND SEMICONDUCTOR DEVICE RESULTING FROM THE SAME PROCESS

Application Number: 20130149838
Publication Date: 2013-06-13
Inventor: STMICROELECTRONICS S.R.L.,

A process for manufacturing a semiconductor device envisages the steps of: providing a semiconductor material body having at least one deep trench that extends through said body of semiconductor material starting from a top surface thereof; and filling the deep trench via an epitaxial growth of semiconductor material, thereby forming a columnar structure within the body of semiconductor material. The manufacturing process further envisages the step of modulating the epitaxial growth by means of ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Application Number: 20130149837
Publication Date: 2013-06-13
Inventor: RENESAS ELECTRONICS CORPORATION,

To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a ...

METHOD OF DOUBLE-SIDED PATTERNING

Application Number: 20130149836
Publication Date: 2013-06-13
Inventor: Shanghai Hua Hong Nec Electronics Co., Ltd.,

A method of double-sided patterning including positioning a first silicon wafer with its back side facing upwards and forming one or more deep trenches serving as alignment marks on the back side of the first silicon wafer; performing alignment with respect to the alignment marks and forming a back-side pattern on the first silicon wafer; depositing a polishing stop layer on the back side of the first silicon wafer; flipping over the first silicon wafer and bonding its back side with the front ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Application Number: 20130149835
Publication Date: 2013-06-13
Inventor: Samsung Electronics Co., Ltd.,

A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation ...

Methods Of Forming Memory Cells, And Methods Of Patterning Chalcogenide-Containing Stacks

Application Number: 20130149834
Publication Date: 2013-06-13
Inventor: MICRON TECHNOLOGY INC.,

Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed over the chalcogenide. Sacrificial material is formed over the top electrode material. A plurality of memory cell structures is formed by etching through the sacrificial material, top electrode material and chalcogenide. Each of the memory cell structures has a cap of the sacrificial material thereover. The etching forms polymeric residue ...

Methods of Manufacturing Semiconductor Devices

Application Number: 20130149833
Publication Date: 2013-06-13
Inventor: Samsung Electronics Co., Ltd.,

A method of manufacturing a semiconductor device, the method including: preparing a semiconductor substrate including a mold layer and a support layer disposed on the mold layer; forming multiple holes that pass through the mold layer and the support layer; forming multiple bottom electrodes in the holes; exposing at least a portion of the bottom electrodes by removing at least a portion of the mold layer; removing a portion of the bottom electrodes from an exposed surface of the bottom ...

TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR

Application Number: 20130149832
Publication Date: 2013-06-13
Inventor: International Business Machines Corporation,

Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance C_cb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance R_band a dielectric spacer between the extrinsic base layer and ...

METHODS FOR FABRICATING BIPOLAR TRANSISTORS WITH IMPROVED GAIN

Application Number: 20130149831
Publication Date: 2013-06-13
Inventors: Lin, Xin; Blomberg, Daniel J.; Zuo, Jiang-Kai

Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration C_FE, and a second emitter (SE) portion (42-2) of a second dopant concentration C_SE. Preferably C_SE≧C_FE. The SE portion ...

METHODS OF FORMING FIELD EFFECT TRANSISTORS HAVING SILICON-GERMANIUM SOURCE/DRAIN REGIONS THEREIN

Application Number: 20130149830
Publication Date: 2013-06-13
Inventors: Utomo, Henry K.; Lee, Seung-Chul; An, Chul-Wan; RHEE, Hwa-Sung; Kim, Seong-Dong

Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches. Silicon germanium (SiGe) source and drain regions may be formed using an epitaxial growth process. During this growth process, the bottoms and sidewalls of the trenches may be used as “seeds” for the silicon germanium growth. An ...

DUAL NSD IMPLANTS FOR REDUCED RSD IN AN NMOS TRANSISTOR

Application Number: 20130149829
Publication Date: 2013-06-13
Inventor: Texas Instruments Incorporated,

In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus ...

GaN-based Semiconductor Element and Method of Manufacturing the Same

Application Number: 20130149828
Publication Date: 2013-06-13
Inventor: Furukawa Electric Co., Ltd.,

Provided is a GaN series semiconductor element, which is capable of obtaining an adequate normally-off characteristic, and a manufacturing method thereof.

In a GaN series semiconductor element that comprises an operating layer comprising a GaN series compound semiconductor, a gate insulating film that is formed on the operating layer, and a gate electrode that is formed on the gate insulating film, the gate insulating is a SiO₂film of which an infrared ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

Application Number: 20130149827
Publication Date: 2013-06-13
Inventor: FUJITSU SEMICONDUCTOR LIMITED,

A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first ...

FinFETs with Multiple Fin Heights

Application Number: 20130149826
Publication Date: 2013-06-13
Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.,

An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Application Number: 20130149825
Publication Date: 2013-06-13
Inventor: Renesas Electronics Corporation,

A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed to be P-type. The protection circuit includes a planar gate horizontal type offset P-channel MOSFET and the conduction type of the gate electrode is assumed to be ...