<?xml version='1.0' encoding='UTF-8'?><rss xmlns:atom="http://www.w3.org/2005/Atom" xmlns:openSearch="http://a9.com/-/spec/opensearchrss/1.0/" xmlns:blogger="http://schemas.google.com/blogger/2008" xmlns:georss="http://www.georss.org/georss" xmlns:gd="http://schemas.google.com/g/2005" xmlns:thr="http://purl.org/syndication/thread/1.0" version="2.0"><channel><atom:id>tag:blogger.com,1999:blog-4707460742463837792</atom:id><lastBuildDate>Fri, 01 Nov 2024 11:35:21 +0000</lastBuildDate><title>Passion for processor</title><description></description><link>http://passionprocessor.blogspot.com/</link><managingEditor>noreply@blogger.com (home50005)</managingEditor><generator>Blogger</generator><openSearch:totalResults>28</openSearch:totalResults><openSearch:startIndex>1</openSearch:startIndex><openSearch:itemsPerPage>25</openSearch:itemsPerPage><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-7602407150708284650</guid><pubDate>Fri, 26 Jun 2009 05:44:00 +0000</pubDate><atom:updated>2009-06-25T22:44:26.554-07:00</atom:updated><title>Intel Shows First Working Moorestown Prototypes</title><description>&lt;h5 align=&quot;justify&quot;&gt;&amp;#160;&lt;/h5&gt;  &lt;p align=&quot;justify&quot;&gt;Moorestown is a chip platform designed for handheld computers that Intel calls mobile Internet devices (MIDs). The heart of Moorestown is a more power-efficient version of the Atom processor, named Lincroft, which is paired with a chipset called Langwell. Intel claims Moorestown uses one-fiftieth the idle power of its predecessor, the Menlow platform. The new platform is available with a range of wireless options, including Wi-Fi, WiMax and 3G cellular connectivity.Engineers managed to get the three devices working and ready for Computex in less than two months, a source familiar with the situation said, adding that Intel originally hoped to show five working prototypes at the show.&lt;/p&gt;  &lt;p align=&quot;justify&quot;&gt;Anand Chandrasekher, the senior vice president of Intel&#39;s ultra mobility group, showed off a handful of sleek prototype mobile devices containing its upcoming Moorestown platform at the Computex exhibition in Taipei on Thursday.During his speech, Chandrasekher was joined on stage by executives from hardware makers Inventec Appliances, Quanta Computer and Elektrobit, who all have working handheld devices based on the chips. The devices were all running the Moblin 2.0 version of Linux and are expected to hit the market early next year, company executives said.While Moorestown is nearing volume production, the current MID platform -- called Menlow -- continues to be used in new designs, a trend that is likely to continue into next year and overlap with the availability of Moorestown, Chandrasekher said.&lt;/p&gt;  </description><link>http://passionprocessor.blogspot.com/2009/06/intel-shows-first-working-moorestown.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-3611613011194700074</guid><pubDate>Fri, 26 Jun 2009 05:43:00 +0000</pubDate><atom:updated>2009-06-25T22:43:33.280-07:00</atom:updated><title>Hynix Agrees to Pay Rambus $397 Mln Settlement</title><description>&lt;h5 align=&quot;justify&quot;&gt;&amp;#160;&lt;/h5&gt;  &lt;p align=&quot;justify&quot;&gt;&lt;img alt=&quot;&quot; src=&quot;https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjw1N9oauiEYNXnn042BLadHXPBR_eU83ym_71jj34LFAN_KFCmkiLscgSn5U6PSL4PJHEAfNn0OKGY5W0guc_AwNz_OSH6KOl26kR0mDlVSYJM8H2SCJVsHBxESmCVSgoYgidJ00U6CeZr/s200/lovelle-mixon-undated-police-mugshot.jpg&quot; border=&quot;0&quot; /&gt;The decade-old patent infringement battle between Rambus and, well, pretty much everybody has taken another step towards closure, with the U.S. District Court for the North District of California entering a final judgment against Hynix for a total of $397 million. Of that figure, $134 million will cover patent infringement between December 31, 2005, while another $215 million will cover infringement from January 1, 2006, through the end of January 2009. Rambus was also awarded another $48 million in interest.&amp;quot;We are pleased with the Court&#39;s decision and are gratified by the tremendous time and energy the Court has dedicated to this matter,&amp;quot; said Rambus senior VP and general counsel Thomas Lavelle, in a statement. &amp;quot;Though this case has been long and arduous, we remain steadfast in our commitment to seek fair compensation for the use of our patented innovations.&amp;quot; &lt;/p&gt;  &lt;p align=&quot;justify&quot;&gt;Hynix, for its part, has complied with the orders of the court, but says it disagrees with the judgement and may pursue an appeal to the Federal Circuit, and notes that another court found Rambus destroyed evidence, and the U.S. Patent and Trademark Office recently issues rulings finding Rambus&#39;s patents invalid. Moving forward, Hynix will have to pay Rambus royalties on net sales of particular memory products from January 31, 2009, through Paril 18, 2010: the amounts are 1 percent for SDR SDRAM products and 4.25 percent for DDR SDRAM products, with the latter rate applying to DDR, DDR2, DDR3, GDDR, GDDR2, GDDR3 SDRAM, and DDR SGRAM products. Moving forward, Hynix will have to pay Rambus royalties on net sales of particular memory products from January 31, 2009, through Paril 18, 2010: the amounts are 1 percent for SDR SDRAM products and 4.25 percent for DDR SDRAM products, with the latter rate applying to DDR, DDR2, DDR3, GDDR, GDDR2, GDDR3 SDRAM, and DDR SGRAM products. &lt;/p&gt;  </description><link>http://passionprocessor.blogspot.com/2009/06/hynix-agrees-to-pay-rambus-397-mln.html</link><author>noreply@blogger.com (home50005)</author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjw1N9oauiEYNXnn042BLadHXPBR_eU83ym_71jj34LFAN_KFCmkiLscgSn5U6PSL4PJHEAfNn0OKGY5W0guc_AwNz_OSH6KOl26kR0mDlVSYJM8H2SCJVsHBxESmCVSgoYgidJ00U6CeZr/s72-c/lovelle-mixon-undated-police-mugshot.jpg" height="72" width="72"/><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-6529866274619414427</guid><pubDate>Sat, 06 Jun 2009 11:25:00 +0000</pubDate><atom:updated>2009-06-06T04:25:53.586-07:00</atom:updated><title>AMD Roadmap: New Athlon II&#39;s Coming</title><description>&lt;p&gt;&lt;strong&gt;According to recent AMD documents that we were able to see, AMD is planning to launch a new Athlon series sometime in June of this year.&lt;/strong&gt;&lt;/p&gt;  &lt;p&gt;The AMD roadmap indicated that there will be several flavors of the Athlon II to choose from. When the new CPUs ship, there will be at least a 2, 3 and 4 core Athlon II all based on the same architecture. In fact, the new Athlon II&#39;s are very much based on AMD&#39;s current Phenom II. Although similar to Phenom II, the new Athlon II CPUs will not ship with shared L3 cache, which something that the Phenom II&#39;s do have.&lt;/p&gt;  &lt;p&gt;AMD&#39;s roadmap also indicated that the upcoming Athlon II&#39;s will be based on socket AM3 and support HyperTransport 3.0 and DDR2 and DDR3 memory.&lt;/p&gt;  &lt;p&gt;In terms of frequency, the minimum spec is 2.8 GHz going to the quad-core Athlon II, while the dual-core rings in at 3.0 GHz. The Athlon II&#39;s will also carry a maximum onboard cache of 2 MB.&lt;/p&gt;  &lt;p&gt;Positioning for the new processors seem to indicate that the Phenom brand will take the high end while Athlon II will take much of the mainstream and lower end.&lt;/p&gt;</description><link>http://passionprocessor.blogspot.com/2009/06/amd-roadmap-new-athlon-iis-coming.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-3921676496706851756</guid><pubDate>Sat, 06 Jun 2009 11:23:00 +0000</pubDate><atom:updated>2009-06-06T04:24:53.389-07:00</atom:updated><title>Unlocking AMD CPU Cores Safe Say Mobo Makers</title><description>While browsing through motherboards at Computex, several manufacturers were quick to tell us some details about the recently released dual-core Phenom II CPUs from AMD.&lt;br /&gt;&lt;br /&gt;Two motherboard makers told us at the show that AMD&#39;s new processors are safe when unlocking disabled cores. In fact, one motherboard maker even told us that when you unlock the disabled cores, they run at slower frequencies than the normal cores.&lt;br /&gt;&lt;br /&gt;This is of course all incorrect, and it is indeed not a safe guarantee when you unlock the disabled cores. The reason for this is that the disabled cores are turned off for a reason: they failed factory tests. Cores can fail for any number of reasons, including defects in the silicon, problems running at full frequency, or a bug introduced during manufacturing.&lt;br /&gt;&lt;br /&gt;Both AMD and Intel disable CPU cores for this very reason.&lt;br /&gt;&lt;br /&gt;When you unlock the disabled cores, they will run at full processor frequency, since you cannot run each core at different speeds. While you may see initial gains and benefits from turning a dual-core CPU into a quad-core CPU, you may introduce instability into your system. Things may corrupt, calculate incorrectly or even crash.&lt;br /&gt;&lt;br /&gt;Despite what we were told, we still recommend that if you&#39;re going to unlock disabled cores, do so with caution in mind--there is always a risk that something will go wrong.</description><link>http://passionprocessor.blogspot.com/2009/06/unlocking-amd-cpu-cores-safe-say-mobo.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-2818606745531381420</guid><pubDate>Sat, 06 Jun 2009 11:19:00 +0000</pubDate><atom:updated>2009-06-06T04:23:50.886-07:00</atom:updated><title>AMD launches dual-core Phenom, Athlon CPUs</title><description>AMD has announced two new dual-core desktop processors that should allow PCs to take advantage of faster memory standards, creating faster models.&lt;br /&gt;&lt;br /&gt;The processor maker&#39;s Phenom II X2 550 Black Edition processor, introduced on Tuesday, is its first ever dual-core version of its Phenom II CPU. It is aimed at the more hard-core user, such as professional users, games enthusiasts and other breeds of overclockers.&lt;br /&gt;&lt;br /&gt;Also released on Tuesday, the new 45nm AMD Athlon II X2 250 processor aims to boost the performance of mainstream consumer PCs. AMD said the key improvement is that the dual-core processors in its Phenom range can make use of better standards of memory. Until recently, they were limited to working with DDR2, but now they can work with the newer, faster memory standard DDR3. The improvement stems from being able to support both AM2+ and AM3 boards for DDR2 and DDR3 memory, according to AMD.&lt;br /&gt;&lt;br /&gt;The Athlon II X2 250 has doubled the previous model&#39;s amount of L2 cache for each core, creating a total L2 cache of 2MB. This will provide 3GHz performance in affordable PCs, according to AMD.&lt;br /&gt;&lt;br /&gt;Another performance boost comes from the optimization with Windows 7, AMD said.&lt;br /&gt;&lt;br /&gt;Though the semiconductor market is proving a difficult source of profits for chipmakers, according to Jonathan Cassell, analyst at market researcher iSuppli, the processor market has never been more buoyant. Strong competition is being created by new CPU releases at all levels, from computers for high-end professional users to budget PCs.&lt;br /&gt;&lt;br /&gt;One UK-based system builder put the launch into perspective. &quot;AMD will boast about dual-core architecture and efficiency achievable through 45nm technology,&quot; said Richard Marsden, sales director at RealTime Distribution, a UK distributor which supplies AMD chips to system builders. &quot;But the bottom line is that an AMD machine will give them 3GHz performance at an affordable price.&quot;</description><link>http://passionprocessor.blogspot.com/2009/06/amd-launches-dual-core-phenom-athlon.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-3174866431244611089</guid><pubDate>Thu, 14 May 2009 06:12:00 +0000</pubDate><atom:updated>2009-05-13T23:13:25.048-07:00</atom:updated><title>Intel Processors, the History</title><description>&lt;p style=&quot;line-height: 19.2pt; text-align: justify;&quot;&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Arial&amp;quot;,&amp;quot;sans-serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;Intel was one of the pioneering Microprocessor manufacturers when it created the 4004 processor in 1971. This was followed by the 8080 processor in the late 70&#39;s, which was developed into the 8086 and 8088 processors in 1979. It was only when, in 1981 IBM selected the 8086 processor for its new Personal Computer, the IBM PC, did the Intel processor design gain its opportunity to be used widely.&lt;/span&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Georgia&amp;quot;,&amp;quot;serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;line-height: 19.2pt; text-align: justify;&quot;&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Arial&amp;quot;,&amp;quot;sans-serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;The Intel 8086/8088 range of processors were based upon Complex Instruction Set Computing (CISC) which allows the number of bytes per instruction to vary according to the instruction being processed. This is unlike Reduced Instruction Set Computing (RISC) which has fixed length instructions (typically set at 32 bits each). The architechture pioneered by Intel has become known as &quot;x86&quot; due to the early naming system where processors were called 8086, 80186 (not used in PC&#39;s), 80286, 80386, and 80486.&lt;/span&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Georgia&amp;quot;,&amp;quot;serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;line-height: 19.2pt; text-align: justify;&quot;&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Arial&amp;quot;,&amp;quot;sans-serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;In 1982 Intel introduced the 80286 (or 286) processor. This featured significant enhancements over the 8086/8088 line, mainly by introducing protected mode and the ability to address up to 16 megabytes of memory. The 286 processor was used in the IBM XT range.&lt;/span&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Georgia&amp;quot;,&amp;quot;serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;line-height: 19.2pt; text-align: justify;&quot;&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Arial&amp;quot;,&amp;quot;sans-serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;1985 saw the introduction of the 80386 (or 386), which was the first processor to use 32 bit addressing, allowing it to utilise up to 4 Gigabytes of memory. A cut down version of the 386 known as the 386SX was introduced which had a lower memory throughput, as it could only access 16 megabytes of memory. The 386 processor was manufactured in many different versions and ran at speeds from 16 Mhz through to 40 Mhz.&lt;/span&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Georgia&amp;quot;,&amp;quot;serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;line-height: 19.2pt; text-align: justify;&quot;&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Arial&amp;quot;,&amp;quot;sans-serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;The 80486 processor family was introduced in 1989. It featured little enhancements over than the 386 other than the fact that it had more transistors and could run at higher clock speeds. Like its predecessor the 386, the 486 was offered in budget (486 SX, minus the math co-processor) and standard (486 DX) versions. The 486 initially ran at clock speeds of 25 MHz (SX only) and 33 MHz. As it was developed the 486 was enhanced with a clock doubled processor core (486 DX-2) allowing it to run at speeds of 50, 66 and 75 MHz, and then tripled (DX-4) which ran up to 100 MHz.&lt;/span&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Georgia&amp;quot;,&amp;quot;serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;line-height: 19.2pt; text-align: justify;&quot;&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Arial&amp;quot;,&amp;quot;sans-serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;1993 saw the introduction of the Pentium processor, first at speeds of 60 and 66 MHz. This was the first Intel processor not to use the x86 naming system. This processor was enhanced with MMX instructions in January 1997 and ran up to speeds of 233 Mhz.&lt;/span&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Georgia&amp;quot;,&amp;quot;serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;line-height: 19.2pt; text-align: justify;&quot;&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Arial&amp;quot;,&amp;quot;sans-serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;Intel&#39;s 6&lt;sup&gt;th&lt;/sup&gt;&lt;span class=&quot;apple-converted-space&quot;&gt; &lt;/span&gt;generation processor was introduced as the Pentium Pro in 1995. This ran at speeds of 166, 180 and 200 MHz. What was significant was the integration of the processors 2&lt;sup&gt;nd&lt;/sup&gt;&lt;span class=&quot;apple-converted-space&quot;&gt; &lt;/span&gt;level cache memory onto the processor module itself. This processor was enhanced with MMX instructions in 1997 with its development into the Pentium II. This marked a departure for Intel as it moved away from the old socket method of mounting processors with the introduction of Slot 1. The Pentium II runs at speeds from 233 to 450 MHz. 1998 saw the development of this familiy into the Celeron and Xeon families for the budget and server/workstation markets respectively.&lt;/span&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Georgia&amp;quot;,&amp;quot;serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;text-align: justify;&quot; class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/intel-processors-history.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-1232895275234455709</guid><pubDate>Thu, 14 May 2009 06:07:00 +0000</pubDate><atom:updated>2009-05-13T23:12:45.385-07:00</atom:updated><title>INTERPOSER</title><description>&lt;span class=&quot;Apple-style-span&quot; style=&quot;border-collapse: separate; color: rgb(51, 51, 51); font-family: Georgia; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;&quot;&gt;&lt;div class=&quot;post-body entry-content&quot; style=&quot;margin: 0px 0px 0.75em; line-height: 1.6em;&quot;&gt;&lt;p&gt;A number of Intel Motherboards incorrectly support the Write Back mode of the Intel Pentium OverDrive processor. Because of this you will be unable to successfully upgrade your CPU. However, to rectify this issue, Intel created a chip called the interposer. This chip allows the computer to work around the design errors.&lt;/p&gt;&lt;p&gt;Documentation for installing the interposer should be included with the interposer. If by chance documentation is not included you can find alternate installation help at Intel&#39;s web site (&lt;em&gt;Search for Interposer&lt;/em&gt;).&lt;/p&gt;&lt;/div&gt;&lt;div class=&quot;post-footer&quot; style=&quot;margin: 0.75em 0px; color: rgb(153, 153, 153); text-transform: uppercase; letter-spacing: 0.1em; font-family: &#39;Trebuchet MS&#39;,Trebuchet,Arial,Verdana,sans-serif; font-style: normal; font-variant: normal; font-weight: normal; font-size: 78%; font-size-adjust: none; font-stretch: normal; line-height: 1.4em;&quot;&gt;&lt;br /&gt;&lt;/div&gt;&lt;/span&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/interposer.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-2425322856538498528</guid><pubDate>Thu, 14 May 2009 06:04:00 +0000</pubDate><atom:updated>2009-05-13T23:06:49.616-07:00</atom:updated><title>The AMD Athlon Processors History</title><description>&lt;p style=&quot;line-height: 15pt; text-align: justify;&quot;&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Georgia&amp;quot;,&amp;quot;serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;Amd Athlon Processors History began with the original Athlon Classic, which is the first seventh-generation x86 processor and since it is the first, it remained to be the first performance lead over Intel for a couple of years.&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;line-height: 15pt; text-align: justify;&quot;&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Georgia&amp;quot;,&amp;quot;serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;It showed a lot of promise as it showed superior performance compared to the Pentium 3 which was the champion at that time. The second generation Athlon called The Thunderbird came along in year 2000. It had a speed ranging from 600 to 1400 MHz. AMD replaced the 512 KiB external reduced speed cache used by the Athlon Classic with 256 KiB of on-chip, full speed exclusive cache. The Thunderbird at this time, won over rival Pentium 3 but AMD did not stop there. AMD released The Palomino or the Athlon XP. XP meaning &quot;Extreme Performance&quot;. Then AMD released The Thunderbird which is at 1.8 GHz. Then the fifth generation Athlon came along, Barton core processors, running at the same speed as the Thoroughbred predecessors.&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;line-height: 15pt; text-align: justify;&quot;&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Georgia&amp;quot;,&amp;quot;serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;Finally, the Mobile Athlon XP was introduced. It has lower power consumption, and lower heat production which is basically used for the notebook. AMD is not stopping and is still continuing to improve its processors as to beat it&#39;s rival Intel. See cpu-lab.com for more details on the AMD Processor.&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;line-height: 15pt; text-align: justify;&quot;&gt;&lt;span style=&quot;font-size: 10pt; font-family: &amp;quot;Georgia&amp;quot;,&amp;quot;serif&amp;quot;; color: rgb(51, 51, 51);&quot;&gt;AMD ex CEO Jerry Sanders vision was to create a &quot;virtual gorilla&quot; that would equip AMD to compete with Intel. A couple of years later, AMD released Athlon K7 processor. AMD got lots of benefits working with Motorola as AMD was able to refine copper interconnect manufacturing to the production stage one year earlier than Intel&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;text-align: justify;&quot; class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/amd-athlon-processors-history.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-7983926012545729817</guid><pubDate>Thu, 14 May 2009 06:02:00 +0000</pubDate><atom:updated>2009-05-13T23:03:57.346-07:00</atom:updated><title>Intel vs Amd</title><description>&lt;p style=&quot;text-align: justify;&quot; class=&quot;MsoNormal&quot;&gt;I SUPPOSE YOU COULD SAY we&#39;ve conducted plenty of CPU reviews in our time, but we just can&#39;t bring ourselves to slow things down. The release of Windows Vista and a round of price cuts by AMD prompted us to hatch a devious plan involving Vista, a new test suite full of multithreaded and 64-bit applications, fifteen different CPU configurations, and countless hours of lab testing. That plan has come to fruition in the form of a broad-based comparison of the latest processors from AMD and Intel, ranging from well under $200 to a cool grand, from two slow CPU cores to four fast ones, from the lowly Athlon 64 X2 4400+ and Core 2 Duo E6300 to the astounding Athlon 64 FX-74 and Core 2 Extreme QX6700.&lt;br /&gt;&lt;br /&gt;So, how do the latest processors stack up in Windows Vista? Will a sub-$200 CPU suffice for your needs? Have price cuts allowed the Athlon 64 to catch up to the Core 2 Duo in terms of price-performance? What about power consumption and energy efficiency? Can any of these processors stand up under the weight of killer new games like Supreme Commander? Can I possibly squeeze any more questions into one paragraph? Keep reading for answers to all of these questions and more.&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;The matchups&lt;br /&gt;The setup for this one is fairly simple. We&#39;re directly comparing processors from Intel at AMD at a range of price points. Intel has had a lock on the overall performance lead since the Core 2 Duo first hit the scene, but AMD has made clear its intention to maintain a competitive price-performance ratio. To do so, AMD will have to meet or beat each of the processors in Intel&#39;s current desktop lineup, which looks like so:&lt;br /&gt;Model Clock speed Cores L2 cache (total) Fab process TDP Price&lt;br /&gt;Core 2 Duo E6300 1.83GHz 2 2MB 65nm 65W $183&lt;br /&gt;Core 2 Duo E6400 2.13GHz 2 2MB 65nm 65W $224&lt;br /&gt;Core 2 Duo E6600 2.4GHz 2 4MB 65nm 65W $316&lt;br /&gt;Core 2 Duo E6700 2.66GHz 2 4MB 65nm 65W $530&lt;br /&gt;Core 2 Extreme X6800 2.93GHz 2 4MB 65nm 75W $999&lt;br /&gt;Core 2 Quad Q6600 2.4GHz 4 8MB 65nm 105W $851&lt;br /&gt;Core 2 Extreme QX6700 2.66GHz 4 8MB 65nm 130W $999&lt;br /&gt;&lt;br /&gt;Intel does offer lower cost options like the Core 2 Duo E4300 and its Celeron value-oriented processors, but our list includes the meat of the lineup.&lt;br /&gt;&lt;br /&gt;AMD, on the other hand, offers a dizzying array of Athlon 64 X2 models, from 3600+ to 6000+, generally in increments of 200 (or is it 200+?). Not only that, but AMD often sells multiple products under the same performance-related model number, just to keep smug members of the general public from becoming overconfident. For instance, the Athlon 64 X2 4400+ comes in a 90nm &quot;Toledo&quot; flavor that runs at 2.2GHz, has 1MB of L2 cache per core, and is intended for Socket 939 motherboards. The X2 4400+ also comes in the form of a 65nm chip code-named &quot;Brisbane&quot; that runs at 2.3GHz, has 512K of L2 per core, and slips into Socket AM2 mobos. Several of these features—fab process, clock frequency, cache size, and socket/memory type—may vary within the same model number.&lt;br /&gt;&lt;br /&gt;With that said, we&#39;ve chosen the following members of the Athlon 64 lineup as the most direct competitors to their Core 2 counterparts. Because we live in the now, all of these are newer-style Socket AM2 processors:&lt;br /&gt;Model Clock speed Cores L2 cache (total) Fab process TDP Price&lt;br /&gt;Athlon 64 X2 4400+ 2.3GHz 2 1MB 65nm 65W $170&lt;br /&gt;Athlon 64 X2 5000+ 2.6GHz 2 1MB 65nm 65W $222&lt;br /&gt;Athlon 64 X2 5600+ 2.8GHz 2 2MB 90nm 89W $326&lt;br /&gt;Athlon 64 X2 6000+ 3.0GHz 2 2MB 90nm 125W $459&lt;br /&gt;Athlon 64 FX-70 2.6GHz 4 4MB 90nm 125W x 2 $599&lt;br /&gt;Athlon 64 FX-72 2.8GHz 4 4MB 90nm 125W x 2 $799&lt;br /&gt;Athlon 64 FX-74 3.0GHz 4 4MB 90nm 125W x 2 $999&lt;br /&gt;&lt;br /&gt;As you can see, AMD has a fairly direct answer for most members of the Core 2 range. Things start to get shaky at the high end, where the Athlon 64&#39;s lower performance takes its toll. The Athlon 64 X2 6000+ sells at a discount versus the Core 2 Duo E6700, and AMD has no answer to the Core 2 Extreme X6800, Intel&#39;s fastest dual-core processor. If you match up the two product lines against one another, the results look something like this:&lt;br /&gt;Model Price Model Price&lt;br /&gt;Core 2 Duo E6300 $183 Athlon 64 X2 4400+ $170&lt;br /&gt;Core 2 Duo E6400 $224 Athlon 64 X2 5000+ $222&lt;br /&gt;Core 2 Duo E6600 $316 Athlon 64 X2 5600+ $326&lt;br /&gt;Core 2 Duo E6700 $530 Athlon 64 X2 6000+ $459&lt;br /&gt;Core 2 Quad Q6600 $851 Athlon 64 FX-72 $799&lt;br /&gt;Core 2 Extreme QX6700 $999 Athlon 64 FX-74 $999&lt;br /&gt;&lt;br /&gt;So the comparisons are remarkably direct, by and large.&lt;br /&gt;&lt;br /&gt;These things are never entirely simple, though, so we should roll out some caveats. One of the big ones involves those FX-series processors. You&#39;ll need two of them in order to populate a Quad FX motherboard, so they&#39;re priced (and listed above) in pairs. However, there&#39;s currently only one Quad FX motherboard available, and it costs about $350, which throws the value equation out of whack.&lt;br /&gt;&lt;br /&gt;The value equation sometimes goes off-kilter the other way when AMD employs guerrilla price-war tactics like selling the Athlon 64 X2 4600+ for $125.99 on Newegg, well below the slower 4400+. AMD has several of these &quot;Crazy Hector&quot; deals going at Newegg right now, and none of them seem to involve the Athlon 64 models we&#39;ve identified as direct competitors to specific Core 2 Duo models. That&#39;s probably an intentional facet of AMD&#39;s strategy. This practice throws a wrench in our nice, neat comparsion, but there&#39;s little we can do other than tell you about it.&lt;br /&gt;&lt;br /&gt;One other thing we should tell you about is why we&#39;ve included two versions of the Athlon 64 X2 5000+ in our testing. Regular readers may recall that we&#39;ve already tested the 65nm version of the 5000+ against its 90nm predecessor and found that the 65nm one had lower power consumption. But the 65nm version also has a slower L2 cache, so we&#39;ve tested the 65nm and 90nm chips head to head to see how the &lt;/p&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/intel-vs-amd.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-6467754077599002679</guid><pubDate>Wed, 13 May 2009 08:23:00 +0000</pubDate><atom:updated>2009-05-13T01:23:46.873-07:00</atom:updated><title>Intel® Core™ i7 Processor Extreme Edition</title><description>&lt;p class=&quot;MsoNormal&quot;&gt;&lt;br /&gt;Wield the ultimate gaming weapon&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Conquer the world of extreme gaming with the fastest performing processor on the planet: the Intel® Core™ i7 processor Extreme Edition.¹ With faster, intelligent multi-core technology that accelerates performance to match your workload, it delivers an incredible breakthrough in gaming performance.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;But performance doesn&#39;t stop at gaming. You&#39;ll multitask 25 percent faster and unleash incredible digital media creation with up to 79 percent faster video encoding and up to 46 percent faster image rendering, plus incredible performance for photo retouching and editing.¹&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;In fact, you&#39;ll experience maximum performance for whatever you do, thanks to the combination of Intel® Turbo Boost technology² and Intel® Hyper-Threading technology (Intel® HT technology)³, which activates full processing power exactly where and when you need it most.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;PRODUCT INFORMATION&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;3.20 GHz core speed&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;8 processing threads with Intel® HT technology&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;8 MB of Intel® Smart Cache&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;3 Channels of DDR3 1066 MHz memory&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;FEATURES AND BENEFITS&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Get extreme with your gaming and advanced multimedia.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Intel Core i7 processors deliver an incredible breakthrough in quad-core performance and feature the latest innovations in processor technologies:&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Intel® Turbo Boost technology maximizes speed for demanding applications, dynamically accelerating performance to match your workload-more performance when you need it the most.²&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Intel® Hyper-Threading technology enables highly threaded applications to get more work done in parallel. With 8 threads available to the operating system, multi-tasking becomes even easier.³&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Intel® Smart Cache provides a higher-performance, more efficient cache subsystem. Optimized for industry leading multi-threaded games.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Intel® QuickPath Interconnect is designed for increased bandwidth and low latency. It can achieve data transfer speeds as high as 25.6 GB/sec with the Extreme Edition processor.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Integrated memory controller enables three channels of DDR3 1066 MHz memory, resulting in up to 25.6 GB/sec memory bandwidth. This memory controller&#39;s lower latency and higher memory bandwidth delivers amazing performance for data-intensive applications.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Intel® HD Boost significantly improves a broad range of multimedia and compute-intensive applications. The 128-bit SSE instructions are issued at a throughput rate of one per clock cycle, allowing a new level of processing efficiency with SSE4 optimized applications.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/intel-core-i7-processor-extreme-edition.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-8533147615590787200</guid><pubDate>Wed, 13 May 2009 08:21:00 +0000</pubDate><atom:updated>2009-05-13T01:23:00.529-07:00</atom:updated><title>Intel® Core™2 Quad Processors</title><description>&lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;&quot;&gt;&lt;!--[if gte vml 1]&gt;&lt;v:shapetype id=&quot;_x0000_t75&quot; coordsize=&quot;21600,21600&quot; spt=&quot;75&quot; preferrelative=&quot;t&quot; path=&quot;m@4@5l@4@11@9@11@9@5xe&quot; filled=&quot;f&quot; stroked=&quot;f&quot;&gt;  &lt;v:stroke joinstyle=&quot;miter&quot;&gt;  &lt;v:formulas&gt;   &lt;v:f eqn=&quot;if lineDrawn pixelLineWidth 0&quot;&gt;   &lt;v:f eqn=&quot;sum @0 1 0&quot;&gt;   &lt;v:f eqn=&quot;sum 0 0 @1&quot;&gt;   &lt;v:f eqn=&quot;prod @2 1 2&quot;&gt;   &lt;v:f eqn=&quot;prod @3 21600 pixelWidth&quot;&gt;   &lt;v:f eqn=&quot;prod @3 21600 pixelHeight&quot;&gt;   &lt;v:f eqn=&quot;sum @0 0 1&quot;&gt;   &lt;v:f eqn=&quot;prod @6 1 2&quot;&gt;   &lt;v:f eqn=&quot;prod @7 21600 pixelWidth&quot;&gt;   &lt;v:f eqn=&quot;sum @8 21600 0&quot;&gt;   &lt;v:f eqn=&quot;prod @7 21600 pixelHeight&quot;&gt;   &lt;v:f eqn=&quot;sum @10 21600 0&quot;&gt;  &lt;/v:formulas&gt;  &lt;v:path extrusionok=&quot;f&quot; gradientshapeok=&quot;t&quot; connecttype=&quot;rect&quot;&gt;  &lt;o:lock ext=&quot;edit&quot; aspectratio=&quot;t&quot;&gt; &lt;/v:shapetype&gt;&lt;v:shape id=&quot;Picture_x0020_19&quot; spid=&quot;_x0000_i1025&quot; type=&quot;#_x0000_t75&quot; alt=&quot;Intel® Core™2 Quad processor&quot; style=&quot;&#39;width:46.5pt;height:57pt;&quot;&gt;  &lt;v:imagedata src=&quot;file:///D:\DOCUME~1\ASWATH~1.STO\LOCALS~1\Temp\msohtmlclip1\01\clip_image001.gif&quot; title=&quot;Intel® Core™2 Quad processor&quot;&gt; &lt;/v:shape&gt;&lt;![endif]--&gt;&lt;!--[if !vml]--&gt;&lt;img src=&quot;file:///D:/DOCUME%7E1/ASWATH%7E1.STO/LOCALS%7E1/Temp/msohtmlclip1/01/clip_image001.gif&quot; alt=&quot;Intel® Core™2 Quad processor&quot; shapes=&quot;Picture_x0020_19&quot; height=&quot;76&quot; width=&quot;62&quot; /&gt;&lt;!--[endif]--&gt;&lt;/span&gt;`Introducing Intel® Core™2 Quad processor for notebook and desktop PCs, designed to handle massive compute and visualization workloads enabled by powerful multi-core technology. Optimized for the longest possible battery life without compromise to performance, Intel Core 2 Quad processors for notebooks allow you to stay unwired longer while running the most compute-intensive applications.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Providing all the bandwidth you need for next-generation highly-threaded applications, the latest four-core Intel Core 2 Quad processors are built on 45nm Intel® Core™ microarchitecture enabling faster, cooler, and quieter mobile and desktop PC and workstation experiences.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Plus, with optional Intel® vPro™ technology, you have the ability to remotely isolate, diagnose, and repair infected desktop and mobile workstations wirelessly and outside of the firewall, even if the PC is off, or the OS is unresponsive.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;FEATURES AND BENEFITS&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;With four processing cores, up to 12MB of shared L2 cache,¹ and up to 1066 MHz Front Side Bus for notebooks, and up to 12MB of L2 cache² and up to 1333 MHz Front Side Bus for desktops, the Intel Core 2 Quad processor delivers amazing performance and power efficiency enabled by the all new hafnium-based circuitry of 45nm Intel Core microarchitecture.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Whether you&#39;re encoding, rendering, editing, or streaming HD multimedia in the office or on the go, power your most demanding applications with notebooks and desktops based on the Intel Core 2 Quad processor.&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Plus, with these processors you get great Intel® technologies built in:&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Intel® Wide Dynamic Execution, enabling delivery of more instructions per clock cycle to improve execution time and energy efficiency&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Intel® Intelligent Power Capability, designed to deliver more energy-efficient performance&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Intel® Virtualization Technology (Intel® VT)&lt;a href=&quot;javascript:openWin(&#39;/technology/product/demos/vt/demo.htm&#39;,&#39;752&#39;,&#39;548&#39;,&#39;no&#39;);&quot;&gt;,&lt;/a&gt; enabling greater security, manageability, and utilization&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Dual Intel® Dynamic Acceleration technology, improving four-core performance by utilizing power headroom of idle cores by dynamically boosting frequency of active cores&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Intel® Smart Memory Access, improving system performance by optimizing the use of the available data bandwidth&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Larger Intel® Advanced Smart Cache optimized for multi-core processors, providing a higher-performance, more efficient cache subsystem&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Intel® Advanced Digital Media Boost, accelerating a broad range of applications along with Intel® HD Boost utilizing new SSE4 instructions for even greater multimedia performance&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Future ready, designed to perform in highly threaded programs with powerful Intel® multi-core technology&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;Desktop processor specifications&lt;/p&gt;  &lt;table class=&quot;MsoNormalTable&quot; style=&quot;&quot; border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot;&gt;  &lt;tbody&gt;&lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Processor NumberΔ&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Cache&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Clock Speed&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Front Side Bus&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td colspan=&quot;8&quot; style=&quot;border-style: none none solid; border-color: -moz-use-text-color -moz-use-text-color rgb(204, 204, 204); border-width: medium medium 1pt; padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;45 nm&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Q9650&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot; nowrap=&quot;nowrap&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;12MB L2&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;3 GHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;1333 MHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Q9550&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot; nowrap=&quot;nowrap&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;12MB L2&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;2.83 GHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;1333 MHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Q9450&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot; nowrap=&quot;nowrap&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;12MB L2&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;2.66 GHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;1333 MHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Q9400&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot; nowrap=&quot;nowrap&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;6MB L2&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;2.66 GHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;1333 MHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Q9300&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot; nowrap=&quot;nowrap&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;6MB L2&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;2.50 GHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;1333 MHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Q9100&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot; nowrap=&quot;nowrap&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;12MB L2&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;2.26 GHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;1066 MHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Q8200&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot; nowrap=&quot;nowrap&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;4MB L2&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;2.33 GHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;1333 MHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td colspan=&quot;8&quot; style=&quot;border-style: none none solid; border-color: -moz-use-text-color -moz-use-text-color rgb(204, 204, 204); border-width: medium medium 1pt; padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;65 nm&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Q6700&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot; nowrap=&quot;nowrap&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;8MB L2&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;2.66 GHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;1066 MHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Q6600&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot; nowrap=&quot;nowrap&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;8MB L2&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;2.40 GHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;1066 MHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;  &lt;/tr&gt; &lt;/tbody&gt;&lt;/table&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/intel-core2-quad-processors.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-8274323438746565872</guid><pubDate>Wed, 13 May 2009 08:20:00 +0000</pubDate><atom:updated>2009-05-13T01:21:34.454-07:00</atom:updated><title>Intel® IXP2325 Network Processor</title><description>&lt;p class=&quot;MsoNormal&quot;&gt;The Intel® IXP2325 network processor extends Intel&#39;s fully programmable architecture to new, lower cost/performance points for access and edge applications, including broadband access devices, wireless infrastructure systems, routers and multi-service switches.&lt;br /&gt;&lt;br /&gt;To meet today&#39;s and tomorrow&#39;s demanding dataplane performance requirements, the IXP2325 network processor provides a powerful, integrated control plane processor in the same chip. The high-speed core (900 MHz) incorporates advanced I/O and memory features, enabling customers to eliminate an external control plane processor in many applications. Additional hardware-assisted features in the IXP2325 network processor increase performance and simplify development.&lt;/p&gt;  &lt;table class=&quot;MsoNormalTable&quot; style=&quot;&quot; border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot;&gt;  &lt;tbody&gt;&lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Features and benefits&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt; &lt;/tbody&gt;&lt;/table&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;  &lt;table class=&quot;MsoNormalTable&quot; style=&quot;&quot; border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot;&gt;  &lt;tbody&gt;&lt;tr style=&quot;height: 3pt;&quot;&gt;   &lt;td style=&quot;padding: 0in; height: 3pt;&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;&quot;&gt;&lt;!--[if gte vml 1]&gt;&lt;v:shapetype id=&quot;_x0000_t75&quot; coordsize=&quot;21600,21600&quot; spt=&quot;75&quot; preferrelative=&quot;t&quot; path=&quot;m@4@5l@4@11@9@11@9@5xe&quot; filled=&quot;f&quot; stroked=&quot;f&quot;&gt;    &lt;v:stroke joinstyle=&quot;miter&quot;&gt;    &lt;v:formulas&gt;     &lt;v:f eqn=&quot;if lineDrawn pixelLineWidth 0&quot;&gt;     &lt;v:f eqn=&quot;sum @0 1 0&quot;&gt;     &lt;v:f eqn=&quot;sum 0 0 @1&quot;&gt;     &lt;v:f eqn=&quot;prod @2 1 2&quot;&gt;     &lt;v:f eqn=&quot;prod @3 21600 pixelWidth&quot;&gt;     &lt;v:f eqn=&quot;prod @3 21600 pixelHeight&quot;&gt;     &lt;v:f eqn=&quot;sum @0 0 1&quot;&gt;     &lt;v:f eqn=&quot;prod @6 1 2&quot;&gt;     &lt;v:f eqn=&quot;prod @7 21600 pixelWidth&quot;&gt;     &lt;v:f eqn=&quot;sum @8 21600 0&quot;&gt;     &lt;v:f eqn=&quot;prod @7 21600 pixelHeight&quot;&gt;     &lt;v:f eqn=&quot;sum @10 21600 0&quot;&gt;    &lt;/v:formulas&gt;    &lt;v:path extrusionok=&quot;f&quot; gradientshapeok=&quot;t&quot; connecttype=&quot;rect&quot;&gt;    &lt;o:lock ext=&quot;edit&quot; aspectratio=&quot;t&quot;&gt;   &lt;/v:shapetype&gt;&lt;v:shape id=&quot;Picture_x0020_1&quot; spid=&quot;_x0000_i1033&quot; type=&quot;#_x0000_t75&quot; alt=&quot;http://www.intel.com/sites/templates/pix/spacer.gif&quot; style=&quot;&#39;width:.75pt;&quot;&gt;    &lt;v:imagedata src=&quot;file:///D:\DOCUME~1\ASWATH~1.STO\LOCALS~1\Temp\msohtmlclip1\01\clip_image001.gif&quot; title=&quot;spacer&quot;&gt;   &lt;/v:shape&gt;&lt;![endif]--&gt;&lt;!--[if !vml]--&gt;&lt;img src=&quot;file:///D:/DOCUME%7E1/ASWATH%7E1.STO/LOCALS%7E1/Temp/msohtmlclip1/01/clip_image002.gif&quot; alt=&quot;http://www.intel.com/sites/templates/pix/spacer.gif&quot; shapes=&quot;Picture_x0020_1&quot; height=&quot;4&quot; width=&quot;1&quot; /&gt;&lt;!--[endif]--&gt;&lt;/span&gt;&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt; &lt;/tbody&gt;&lt;/table&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;  &lt;table class=&quot;MsoNormalTable&quot; style=&quot;&quot; border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;1&quot;&gt;  &lt;tbody&gt;&lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Two integrated programmable microengines (MEv2) with 8K   instruction program stores running at 600 MHz&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Flexible multi-threaded RISC processors can be programmed   to deliver intelligent transmit and receive processing, with robust software   development environment for rapid product development&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Integrated Intel XScale® core:&lt;/p&gt;   &lt;table class=&quot;MsoNormalTable&quot; style=&quot;&quot; border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot;&gt;    &lt;tbody&gt;&lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 10.5pt;&quot; valign=&quot;top&quot; width=&quot;14&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;&quot;&gt;&lt;!--[if gte vml 1]&gt;&lt;v:shape id=&quot;Picture_x0020_2&quot; spid=&quot;_x0000_i1032&quot; type=&quot;#_x0000_t75&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; style=&quot;&#39;width:9.75pt;height:8.25pt;visibility:visible;mso-wrap-style:square&#39;&quot;&gt;      &lt;v:imagedata src=&quot;file:///D:\DOCUME~1\ASWATH~1.STO\LOCALS~1\Temp\msohtmlclip1\01\clip_image003.gif&quot; title=&quot;bullet_smblk&quot;&gt;     &lt;/v:shape&gt;&lt;![endif]--&gt;&lt;!--[if !vml]--&gt;&lt;img src=&quot;file:///D:/DOCUME%7E1/ASWATH%7E1.STO/LOCALS%7E1/Temp/msohtmlclip1/01/clip_image003.gif&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; shapes=&quot;Picture_x0020_2&quot; height=&quot;11&quot; width=&quot;13&quot; /&gt;&lt;!--[endif]--&gt;&lt;/span&gt;&lt;/p&gt;     &lt;/td&gt;     &lt;td style=&quot;padding: 0in;&quot; valign=&quot;top&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;32 Kbytes - Instruction cache&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 10.5pt;&quot; valign=&quot;top&quot; width=&quot;14&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;&quot;&gt;&lt;!--[if gte vml 1]&gt;&lt;v:shape id=&quot;Picture_x0020_3&quot; spid=&quot;_x0000_i1031&quot; type=&quot;#_x0000_t75&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; style=&quot;&#39;width:9.75pt;height:8.25pt;visibility:visible;mso-wrap-style:square&#39;&quot;&gt;      &lt;v:imagedata src=&quot;file:///D:\DOCUME~1\ASWATH~1.STO\LOCALS~1\Temp\msohtmlclip1\01\clip_image003.gif&quot; title=&quot;bullet_smblk&quot;&gt;     &lt;/v:shape&gt;&lt;![endif]--&gt;&lt;!--[if !vml]--&gt;&lt;img src=&quot;file:///D:/DOCUME%7E1/ASWATH%7E1.STO/LOCALS%7E1/Temp/msohtmlclip1/01/clip_image003.gif&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; shapes=&quot;Picture_x0020_3&quot; height=&quot;11&quot; width=&quot;13&quot; /&gt;&lt;!--[endif]--&gt;&lt;/span&gt;&lt;/p&gt;     &lt;/td&gt;     &lt;td style=&quot;padding: 0in;&quot; valign=&quot;top&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;32 Kbytes - Data cache&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 10.5pt;&quot; valign=&quot;top&quot; width=&quot;14&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;&quot;&gt;&lt;!--[if gte vml 1]&gt;&lt;v:shape id=&quot;Picture_x0020_4&quot; spid=&quot;_x0000_i1030&quot; type=&quot;#_x0000_t75&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; style=&quot;&#39;width:9.75pt;height:8.25pt;visibility:visible;mso-wrap-style:square&#39;&quot;&gt;      &lt;v:imagedata src=&quot;file:///D:\DOCUME~1\ASWATH~1.STO\LOCALS~1\Temp\msohtmlclip1\01\clip_image003.gif&quot; title=&quot;bullet_smblk&quot;&gt;     &lt;/v:shape&gt;&lt;![endif]--&gt;&lt;!--[if !vml]--&gt;&lt;img src=&quot;file:///D:/DOCUME%7E1/ASWATH%7E1.STO/LOCALS%7E1/Temp/msohtmlclip1/01/clip_image003.gif&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; shapes=&quot;Picture_x0020_4&quot; height=&quot;11&quot; width=&quot;13&quot; /&gt;&lt;!--[endif]--&gt;&lt;/span&gt;&lt;/p&gt;     &lt;/td&gt;     &lt;td style=&quot;padding: 0in;&quot; valign=&quot;top&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;At 900 MHz&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;   &lt;/tbody&gt;&lt;/table&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Embedded 32-bit RISC core for high performance processing   of complex algorithms, route table maintenance and system-level management   functions. Lowers system cost by eliminating external host processor.&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Integrated 512 Kbytes L2 push cache performance&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Improves CPU performance and MEv2 to Intel XScale core and   PCI to Intel XScale core communication&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Two unidirectional 32-bit media interfaces (Rx and Tx)   programmable as SPI-3 or UTOPIA&lt;br /&gt; &lt;br /&gt;  Each path configurable for 4x8-bit, 2x16-bit, 1x32-bit or combinations of 8-   &amp;amp; 16-bit data paths&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Supports industry standard cell and packet interfaces to   media and fabric devices; simplifies design and interface to custom ASIC   devices&lt;br /&gt; &lt;br /&gt;  Supports up to 127 ports using a 16-bit UTOPIA-2 MPHY mode&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Two integrated Gigabit Ethernet MACs&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Lowers system cost, power and board real estate&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Two integrated 10/100 Ethernet MACs&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Can be used as debugging ports or control signal ports.   Lowers system cost, power and board real estate.&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Integrated high speed serial controller:&lt;/p&gt;   &lt;table class=&quot;MsoNormalTable&quot; style=&quot;&quot; border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot;&gt;    &lt;tbody&gt;&lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 10.5pt;&quot; valign=&quot;top&quot; width=&quot;14&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;&quot;&gt;&lt;!--[if gte vml 1]&gt;&lt;v:shape id=&quot;Picture_x0020_5&quot; spid=&quot;_x0000_i1029&quot; type=&quot;#_x0000_t75&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; style=&quot;&#39;width:9.75pt;height:8.25pt;visibility:visible;mso-wrap-style:square&#39;&quot;&gt;      &lt;v:imagedata src=&quot;file:///D:\DOCUME~1\ASWATH~1.STO\LOCALS~1\Temp\msohtmlclip1\01\clip_image003.gif&quot; title=&quot;bullet_smblk&quot;&gt;     &lt;/v:shape&gt;&lt;![endif]--&gt;&lt;!--[if !vml]--&gt;&lt;img src=&quot;file:///D:/DOCUME%7E1/ASWATH%7E1.STO/LOCALS%7E1/Temp/msohtmlclip1/01/clip_image003.gif&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; shapes=&quot;Picture_x0020_5&quot; height=&quot;11&quot; width=&quot;13&quot; /&gt;&lt;!--[endif]--&gt;&lt;/span&gt;&lt;/p&gt;     &lt;/td&gt;     &lt;td style=&quot;padding: 0in;&quot; valign=&quot;top&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;256 HDLC channel controller&lt;br /&gt;    (64 channels when configured with dynamic timeslot remap)&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 10.5pt;&quot; valign=&quot;top&quot; width=&quot;14&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;&quot;&gt;&lt;!--[if gte vml 1]&gt;&lt;v:shape id=&quot;Picture_x0020_6&quot; spid=&quot;_x0000_i1028&quot; type=&quot;#_x0000_t75&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; style=&quot;&#39;width:9.75pt;height:8.25pt;visibility:visible;mso-wrap-style:square&#39;&quot;&gt;      &lt;v:imagedata src=&quot;file:///D:\DOCUME~1\ASWATH~1.STO\LOCALS~1\Temp\msohtmlclip1\01\clip_image003.gif&quot; title=&quot;bullet_smblk&quot;&gt;     &lt;/v:shape&gt;&lt;![endif]--&gt;&lt;!--[if !vml]--&gt;&lt;img src=&quot;file:///D:/DOCUME%7E1/ASWATH%7E1.STO/LOCALS%7E1/Temp/msohtmlclip1/01/clip_image003.gif&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; shapes=&quot;Picture_x0020_6&quot; height=&quot;11&quot; width=&quot;13&quot; /&gt;&lt;!--[endif]--&gt;&lt;/span&gt;&lt;/p&gt;     &lt;/td&gt;     &lt;td style=&quot;padding: 0in;&quot; valign=&quot;top&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;ATM-TC&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 10.5pt;&quot; valign=&quot;top&quot; width=&quot;14&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;&quot;&gt;&lt;!--[if gte vml 1]&gt;&lt;v:shape id=&quot;Picture_x0020_7&quot; spid=&quot;_x0000_i1027&quot; type=&quot;#_x0000_t75&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; style=&quot;&#39;width:9.75pt;height:8.25pt;visibility:visible;mso-wrap-style:square&#39;&quot;&gt;      &lt;v:imagedata src=&quot;file:///D:\DOCUME~1\ASWATH~1.STO\LOCALS~1\Temp\msohtmlclip1\01\clip_image003.gif&quot; title=&quot;bullet_smblk&quot;&gt;     &lt;/v:shape&gt;&lt;![endif]--&gt;&lt;!--[if !vml]--&gt;&lt;img src=&quot;file:///D:/DOCUME%7E1/ASWATH%7E1.STO/LOCALS%7E1/Temp/msohtmlclip1/01/clip_image003.gif&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; shapes=&quot;Picture_x0020_7&quot; height=&quot;11&quot; width=&quot;13&quot; /&gt;&lt;!--[endif]--&gt;&lt;/span&gt;&lt;/p&gt;     &lt;/td&gt;     &lt;td style=&quot;padding: 0in;&quot; valign=&quot;top&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;Up to 16xT1/E1/J1 TDM links&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;   &lt;/tbody&gt;&lt;/table&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Performs inverse multiplexing over ATM (IMA), which   provides lower system cost, power and board real estate&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Integrated cryptography accelerator&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Provides up to 200 Mbps bulk encryption (DES/SHA-1)   capability. Supports AES, DES and 3DES encryption algorithms as well as SHA-1   and MD5 hashing algorithms.&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Two industry standard DDR DRAM interfaces:&lt;/p&gt;   &lt;table class=&quot;MsoNormalTable&quot; style=&quot;&quot; border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot;&gt;    &lt;tbody&gt;&lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 10.5pt;&quot; valign=&quot;top&quot; width=&quot;14&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;&quot;&gt;&lt;!--[if gte vml 1]&gt;&lt;v:shape id=&quot;Picture_x0020_8&quot; spid=&quot;_x0000_i1026&quot; type=&quot;#_x0000_t75&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; style=&quot;&#39;width:9.75pt;height:8.25pt;visibility:visible;mso-wrap-style:square&#39;&quot;&gt;      &lt;v:imagedata src=&quot;file:///D:\DOCUME~1\ASWATH~1.STO\LOCALS~1\Temp\msohtmlclip1\01\clip_image003.gif&quot; title=&quot;bullet_smblk&quot;&gt;     &lt;/v:shape&gt;&lt;![endif]--&gt;&lt;!--[if !vml]--&gt;&lt;img src=&quot;file:///D:/DOCUME%7E1/ASWATH%7E1.STO/LOCALS%7E1/Temp/msohtmlclip1/01/clip_image003.gif&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; shapes=&quot;Picture_x0020_8&quot; height=&quot;11&quot; width=&quot;13&quot; /&gt;&lt;!--[endif]--&gt;&lt;/span&gt;&lt;/p&gt;     &lt;/td&gt;     &lt;td style=&quot;padding: 0in;&quot; valign=&quot;top&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;One 64-bit + ECC DDR300 low latency channel (up to 2GB)     optimized for microengine use&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 10.5pt;&quot; valign=&quot;top&quot; width=&quot;14&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;&quot;&gt;&lt;!--[if gte vml 1]&gt;&lt;v:shape id=&quot;Picture_x0020_9&quot; spid=&quot;_x0000_i1025&quot; type=&quot;#_x0000_t75&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; style=&quot;&#39;width:9.75pt;height:8.25pt;visibility:visible;mso-wrap-style:square&#39;&quot;&gt;      &lt;v:imagedata src=&quot;file:///D:\DOCUME~1\ASWATH~1.STO\LOCALS~1\Temp\msohtmlclip1\01\clip_image003.gif&quot; title=&quot;bullet_smblk&quot;&gt;     &lt;/v:shape&gt;&lt;![endif]--&gt;&lt;!--[if !vml]--&gt;&lt;img src=&quot;file:///D:/DOCUME%7E1/ASWATH%7E1.STO/LOCALS%7E1/Temp/msohtmlclip1/01/clip_image003.gif&quot; alt=&quot;http://www.intel.com/design/shared/pix/bullet_smblk.gif&quot; shapes=&quot;Picture_x0020_9&quot; height=&quot;11&quot; width=&quot;13&quot; /&gt;&lt;!--[endif]--&gt;&lt;/span&gt;&lt;/p&gt;     &lt;/td&gt;     &lt;td style=&quot;padding: 0in;&quot; valign=&quot;top&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;One 32-bit + ECC DDR300 low latency channel (up to 1GB)     optimized for the Intel XScale core&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;   &lt;/tbody&gt;&lt;/table&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Memory subsystem supports the network processor   store-and-forward processing model. Separate memory channels for Intel XScale   core and microengines improves data plane and control plane performance.&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;I/O coherency for Intel XScale core DRAM&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Improves performance through accelerated control   plane/data plane communications&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;One industry standard QDR SRAM interface&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Provides industry standard interface for memory subsystem   for look-up tables and access lists, or co-processors (such as CAM/TCAM)&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Asynchronous control interface supports 8- or 16-bit slow   port devices via 16-bit expansion bus&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Provides control interface for connecting to   microprocessor port of PHY devices and flash memory. Provides a direct   connection to DSP via HPI.&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Hardware support for memory access queuing&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Simplifies application development and reduces system cost&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;JTAG support&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Improves hardware debug ability&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Intel® IXA Software Development Kit (SDK)&lt;br /&gt;  Intel® Hardware Development Platform&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: white none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Industry standard AdvancedTCA* form factor hardware   reference design and state of the art development tools improves time to   market via robust hardware and software development tools&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt;  &lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;1752 ball FCBGA 42.5 mm x 42.5 mm package&lt;/p&gt;   &lt;/td&gt;   &lt;td style=&quot;padding: 3.75pt; background: rgb(230, 230, 230) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;&quot; valign=&quot;top&quot;&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;Minimizes board layers, providing easier board layer   routing and lower cost&lt;/p&gt;   &lt;/td&gt;  &lt;/tr&gt; &lt;/tbody&gt;&lt;/table&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/intel-ixp2325-network-processor.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-9064240773054537351</guid><pubDate>Wed, 13 May 2009 08:01:00 +0000</pubDate><atom:updated>2009-05-13T01:20:05.383-07:00</atom:updated><title>Intel® IXP2805 Network Processor</title><description>&lt;p style=&quot;text-align: justify;&quot; class=&quot;MsoNormal&quot;&gt;The Intel® IXP2805 network processor is footprint- and pin compatible with the Intel® IXP28XX product line of network processors, allowing customers an easy migration path for new designs that require higher performance and lower power. The Intel IXP2805 is a highly flexible and programmable network processor with a high-performance parallel processing architecture for processing complex Layer 2 through Layer 7 algorithms, deep packet inspection and filtering, traffic management, and forwarding at wire speed.&lt;br /&gt;&lt;br /&gt;The Intel IXP2805 network processor is supported by a comprehensive development environment including a common set of development tools, libraries, and example designs that can help accelerate time-to-market and enable the addition of new and evolving services to customer applications.&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;text-align: justify;&quot; class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;table class=&quot;MsoNormalTable&quot; style=&quot;width: 426pt; text-align: left; margin-left: 0px; margin-right: 0px;&quot; border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot; width=&quot;568&quot;&gt;  &lt;tbody&gt;&lt;tr style=&quot;&quot;&gt;   &lt;td style=&quot;padding: 0in; width: 426pt;&quot; valign=&quot;top&quot; width=&quot;568&quot;&gt;   &lt;table class=&quot;MsoNormalTable&quot; style=&quot;width: 426pt;&quot; border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot; width=&quot;568&quot;&gt;    &lt;tbody&gt;&lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in 0in 3pt;&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;Product Highlights&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in;&quot;&gt;&lt;br /&gt;&lt;/td&gt;    &lt;/tr&gt;   &lt;/tbody&gt;&lt;/table&gt;   &lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;   &lt;table class=&quot;MsoNormalTable&quot; style=&quot;width: 426pt;&quot; border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot; width=&quot;568&quot;&gt;    &lt;tbody&gt;&lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 426pt;&quot; width=&quot;568&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;Low-power/high-performance solution for a broad range of     Layer 2 through Layer 7 applications&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 426pt;&quot; width=&quot;568&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;Up to 10 Gbps packet forwarding, policing, scheduling,     queue management, and protocol inter-working&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 426pt;&quot; width=&quot;568&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;16 fully programmable multi-threaded microengines     support 25 Giga-operations per second&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 426pt;&quot; width=&quot;568&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;High-performance, low-power 32-bit Intel XScale® core     for processing complex algorithms, route table maintenance, and control     plane and system-level management functions&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 426pt;&quot; width=&quot;568&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;64-million enqueue/dequeue packet operations per second,     enabling deep packet processing of minimum 49-byte Packet-Over-SONET (POS)     packets with no loss of performance&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 426pt;&quot; width=&quot;568&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;Software- and pin-compatible with the Intel® IXP28XX     product line of network processors, preserving customer investments and     enabling evolution of current IXP28XX-based boards and systems&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;    &lt;tr style=&quot;&quot;&gt;     &lt;td style=&quot;padding: 0in; width: 426pt;&quot; width=&quot;568&quot;&gt;     &lt;p class=&quot;MsoNormal&quot;&gt;Industry-standard Advanced Telecom Computing     Architecture*-based (AdvancedTCA*) hardware development platform for rapid     product development and prototyping&lt;/p&gt;     &lt;/td&gt;    &lt;/tr&gt;   &lt;/tbody&gt;&lt;/table&gt;   &lt;/td&gt;  &lt;/tr&gt; &lt;/tbody&gt;&lt;/table&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;  &lt;/div&gt;&lt;p style=&quot;text-align: justify;&quot; class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/p&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/intel-ixp2805-network-processor.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-1448672097405926327</guid><pubDate>Wed, 13 May 2009 08:01:00 +0000</pubDate><atom:updated>2009-05-13T01:01:37.918-07:00</atom:updated><title>2.93GHz Mobile Core 2 Duo waiting for entry</title><description>&lt;span class=&quot;Apple-style-span&quot; style=&quot;border-collapse: separate; color: rgb(51, 51, 51); font-family: Georgia; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;&quot;&gt;2.93GHz Mobile Core 2 Duo&lt;br /&gt;&lt;br /&gt;2.93GHz Mobile Core 2 Duo&lt;br /&gt;Leading chip maker Intel is expected to release a new Core 2 Duo CPU for portable computer systems sometime in Q1 next year. According to details currently made available, the Santa Clara, California-based company is going to deliver a faster-running mobile CPU, raising the performance level of its current high-speed Core 2 Duo processor, the T9600, which was just released last month.&lt;br /&gt;&lt;br /&gt;The upcoming Core 2 Duo mobile CPU is said to deliver a core speed of 2.93GHz, up from the 2.8GHz on the company&#39;s current Core 2 Duo T9600. According to Fudzilla, chip maker Intel will release the T9800 CPU at a yet unannounced date in Q1 2009, by which time some users should have already gotten a chance at Intel&#39;s next-generation desktop CPUs, the Core i7.As with any officially unreleased product, details on the upcoming Intel mobile processor are rather scarce, but we can tell you that, aside from the higher clock rate, the new T9800 CPU is rather similar to Intel&#39;s T9600, as it features the same 1066MHz FSB and 6MB of cache. This means that there&#39;s going to be just a slight difference in performance between the two processors. Even so, some users out there might go the extra mile and choose the upcoming T9800 over the current T9600, despite an expected price tag of $530 at launch.&lt;br /&gt;&lt;br /&gt;Unfortunately, this sums up just about every detail that is currently available on Intel&#39;s upcoming Core 2 Duo mobile processor. Further info should most likely emerge as the official unveiling is drawing near. However, most users will probably be more interested in the company&#39;s next-generation Core i7 processors, built on the Nehalem architecture. These new CPUs are said to deliver a new level of performance for upcoming desktop computer systems, and thus further increase Intel&#39;s market advantage over competitor AMD.&lt;/span&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/293ghz-mobile-core-2-duo-waiting-for.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-4056997918365125988</guid><pubDate>Wed, 13 May 2009 08:00:00 +0000</pubDate><atom:updated>2009-05-13T01:00:57.787-07:00</atom:updated><title>Intel Initiates Shipments of Core i7 Microprocessors.</title><description>&lt;span class=&quot;Apple-style-span&quot; style=&quot;border-collapse: separate; color: rgb(51, 51, 51); font-family: Georgia; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;&quot;&gt;Paul Otellini said during a conference call with financial analysts that the chipmaker has initiated shipments of its new microprocessors based on Nehalem micro-architecture. The new chips will enable higher performance and will also utilize radically different platform architecture that will resemble that of Advanced Micro Devices.&lt;br /&gt;&lt;br /&gt;Intel Core i7/Nehalem Now Shipping&lt;br /&gt;&lt;br /&gt;“I am pleased to announce that we began shipments of our Nehalem product family during the third quarter and expect to formally launch these products in November. Nehalem brings a new micro-architecture and new performance features. This new product family will further extend our performance leadership in microprocessors,” said Mr. Otellini while announcing financial results for the third quarter.&lt;br /&gt;&lt;br /&gt;Mr. Otellini said that despite of economy crisis Intel intends to release its Core i7 as well as Xeon processors based on Nehalem micro-architecture as soon as possible in order to boost demand in certain market segments, which would naturally offset lowering demand from corporate segment in the USA.&lt;br /&gt;&lt;br /&gt;“We are trying to pull them in as fast as possible. I think having those products simply makes us even more competitive and I think they generate some demand in some segments where we haven’t been participating, so that’s one where I feel pretty good about the product line and the sooner we get to it, the better across the board,” said chief executive of Intel Corp.&lt;br /&gt;&lt;br /&gt;The release of Intel Xeon processors powered by Nehalem micro-architecture will particularly improve Intel’s positions on the market of servers, where AMD still can offer a lot of advantages over rival’s offerings. Given that Intel’s desktop processors aimed at professionals and entertainment enthusiasts are already faster than those from AMD, the chip giant only needs new chips in that segment to encourage end-users for upgrades.&lt;br /&gt;&lt;br /&gt;Best Third Quarter Revenue in Its History – Intel&lt;br /&gt;&lt;br /&gt;Intel on Tuesday announced record third-quarter revenue of $10.2 billion along with operating income of $3.1 billion, net income of $2 billion and earnings per share (EPS) of 35 cents.&lt;br /&gt;&lt;br /&gt;“Intel delivered the best third-quarter revenue in its history. We were solidly profitable, with operating income of over $3 billion, reflecting strong across-the-board execution and best-of-class products” said Paul Otellini.&lt;br /&gt;&lt;br /&gt;The company said that strong product portfolio and new product launches will help the company to remain successful amid financial crisis.&lt;br /&gt;&lt;br /&gt;“As we look to Q4, it is hard to know what impact the financial crisis will have on end customer demand. We are confident that our product portfolio, strong cash flow, commitment to deploying new technology and market momentum will allow us to outpace peer companies at a time when business levels are difficult to predict,” the head of Intel promised.&lt;br /&gt;New Chips Set to Boost Performance by 52%&lt;br /&gt;&lt;br /&gt;Documents from Intel Corp. allegedly seen by a web-site earlier this month reportedly mention that Intel Core i7 processor 965 (3.0GHz) delivers 52% speed improvement in 3D games, 41% higher performance in media encoding and editing applications as well as 38% greater 3D rendering speed when compared to Intel Core 2 Extreme QX9770 (3.0GHz). If the information regarding performance improvements is correct, then it means that the new micro-architecture in its first implementation provides roughly 52% more performance at the same clock-speed compared to currently used Core 2 micro-architecture.&lt;br /&gt;&lt;br /&gt;The main micro-architectural enhancement for Intel Core i7/Nehalem that Intel has discussed so far is increased parallelism – the new microprocessors will be able to execute 33% more concurrent micro-ops at the same time. Additional improvements include faster unaligned cache accesses and faster synchronization primitives. In order to exclude situations when execution units stand idle, Intel also implemented new 2nd level branch predictor.&lt;br /&gt;&lt;br /&gt;Another key enhancement of Intel Nehalem is completely redesigned cache sub-system. The new chips will feature 2nd level 512 entry translation look-aside buffer (in addition to 1st level TLB) in order to further reduce the so-called TLB miss rate, a completely new feature on x86 microprocessors. In addition, Intel Nehalem processors (at least, in certain implementations) will have three-level cache hierarchy: 64KB L1 (32KB for data, 32KB for instructions), 256KB L2 cache per core, 8MB L3 cache per processor. Traditionally, Intel chips use inclusive cache policy.&lt;br /&gt;&lt;br /&gt;The Intel Core i7 chips will feature triple-channel DDR3 memory controller (with up to 1333MHz clock-speed supported initially), will use Quick Path Interconnect (QPI) bus and will support multi-threading technology similar with Intel Hyper-Threading that was first unveiled back in 2002 as well as SSE4.2 instructions.&lt;/span&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/intel-initiates-shipments-of-core-i7.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-2809010245351203492</guid><pubDate>Wed, 13 May 2009 07:59:00 +0000</pubDate><atom:updated>2009-05-13T00:59:21.478-07:00</atom:updated><title>Intel thinking use of jet engine&#39;s cooling technique</title><description>&lt;span class=&quot;Apple-style-span&quot; style=&quot;border-collapse: separate; color: rgb(51, 51, 51); font-family: Georgia; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;&quot;&gt;Intel is looking to cool your laptop with the exact same technology that a jet engine does. The issue of burning legs (that’s right, burning legs) has been an issue on the mind of Intel for some time now, and they’re looking to soothe that with their latest breakthrough.&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;Intel jet engine&#39;s cooling technique&lt;br /&gt;Intel has been focusing on the increasing issue of hot thighs with something called Laminar Flow. Laminar Flow occurs when a fluid or gas/air flows in parallel layers, allowing a non-turbulent way to misdirect hot air away from the surface of a jet engine (or laptop). As demonstrated, this technology allows efficient cooling of temperatures upwards of 1,000 °C.A demo of this technology was given at this week’s Intel developer forum in Taiwan by Mooly Eden, Intel’s head of Mobile Platforms Group. “We are licensing it to our customers so they can keep making thinner and thinner laptops,” said Eden.&lt;/span&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/intel-thinking-use-of-jet-engines.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-4283595835053020802</guid><pubDate>Wed, 13 May 2009 07:57:00 +0000</pubDate><atom:updated>2009-05-13T00:58:10.675-07:00</atom:updated><title>Dual-core Atom ready for showtime</title><description>&lt;div style=&quot;text-align: justify; font-weight: bold;&quot;&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;border-collapse: separate; color: rgb(51, 51, 51); font-family: Georgia; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;&quot;&gt;Tranquil PC just announced two new products based around Intel&#39;s upcoming Atom 330 dual-core processor, which Tranquil has confusingly dubbed the Atom2 Z330. We&#39;ll find out soon enough who&#39;s right in their terminology, but cheap-ass speed freaks have more exciting distinctions to worry about. The new processor has dual Atom wafers, for pretty much twice the fun, and Tranquil says that desktop performance is &quot;very very snappy.&quot; They&#39;re celebrating the new processor with the T7-HSG Home Server, which will start shipping on September 30th in very limited supply for £299 (about $528 US). There&#39;s also a DVB-T Media Center in the works, but we&#39;re otherwise short on details.&lt;/span&gt;&lt;/div&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/dual-core-atom-ready-for-showtime.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-5154427815378502791</guid><pubDate>Wed, 13 May 2009 07:55:00 +0000</pubDate><atom:updated>2009-05-13T00:56:05.282-07:00</atom:updated><title>Intel Core i7 920, 940 and 965 models</title><description>&lt;span class=&quot;Apple-style-span&quot; style=&quot;border-collapse: separate; color: rgb(51, 51, 51); font-family: Georgia; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;&quot;&gt;While some companies are already out there promising Core i7-based gear, we haven&#39;t yet heard many official specifics about the actual processors that&#39;ll be at the heart of them. That&#39;s now changed in a pretty big way, however, with some supposedly authentic leaked materials revealing the complete spec list and some pricing details. Apparently, you can expect Core i7 920, 940 and 965 models to roll out in November, with &#39;em clocking in at 2.66GHz, 2.93GHz, and 3.2GHz, respectively. Each, as expected, are quad-core, 45nm processors, and each boast the same 8MB of shared L3 cache, 256kb of L2 cache per core, and TDP rating of 130W. No word on individual unit pricing just yet, but it looks like the Core i7 920 will run $284 in quantities of 1,000, with Core i7 940 upping things considerably to $562, and the &quot;extreme&quot; Core i7 965 demanding a hefty $999.&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;Model number Intel Core i7 920&lt;br /&gt;(mainstream) Intel Core i7 940&lt;br /&gt;(performance) Intel Core i7 965&lt;br /&gt;(extreme)&lt;br /&gt;Clock 2.66GHz 2.93GHz 3.20GHz&lt;br /&gt;Cores 4 4 4&lt;br /&gt;Threads 8 8 8&lt;br /&gt;Process 45nm 45nm 45nm&lt;br /&gt;Socket LGA1366 LGA1366 LGA1366&lt;br /&gt;TDP 130W 130W 130W&lt;br /&gt;L2 cache 256KB per core 256KB per core 256KB per core&lt;br /&gt;L3 cache 8MB shared 8MB shared 8MB shared&lt;br /&gt;Price (in thousand unit quantities) $284 $562 $999&lt;/span&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/intel-core-i7-920-940-and-965-models.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-6218771681153049706</guid><pubDate>Wed, 13 May 2009 07:53:00 +0000</pubDate><atom:updated>2009-05-13T00:55:14.977-07:00</atom:updated><title>The Core 2 Extreme QX9650</title><description>&lt;span class=&quot;Apple-style-span&quot; style=&quot;border-collapse: separate; color: rgb(51, 51, 51); font-family: Georgia; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;&quot;&gt;The latest high-end processor from Intel is the Core 2 Extreme QX9650. It is a quad-core chip running at 3 GHz produced on a 45 nanometer assembly line. It has a total of 12 megabytes of cache on the chip. Here is a complete review, including a summary of the 45 nm production process:&lt;br /&gt;&lt;br /&gt;Penryn Arrives: Core 2 Extreme QX9650 Review&lt;br /&gt;&lt;br /&gt;In this article they were able to boost the memory speed to 1600 MHz and overclock the chip to 3.6 GHz (a 20% increase) without any trouble, which bodes well for the speed of future chips.&lt;br /&gt;&lt;br /&gt;Here are two other announcements:&lt;br /&gt;- Intel’s 45nm Penryn/Yorkfield architecture packs serious punch&lt;br /&gt;- Intel Core 2 Extreme QX9650 - Penryn Ticks Ahead&lt;br /&gt;&lt;br /&gt;The Anandtech article talks about the future: “The other important item to note on the roadmap going forward is that top line in the table - yep, the one that says Bloomfield. Bloomfield is none other than Nehalem, the 45nm successor to Penryn. It’s a brand new architecture complete with an on-die memory controller, SMT (Symmetric Multi-Threading - 2 threads per core) and 8MB of shared cache (probably L3 shared among all four cores). While it’s still a year away, it’s very nice to see it on an Intel roadmap this far in advance of its launch.” That chip will probably crack the billion transistor barrier.&lt;/span&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/core-2-extreme-qx9650.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-2842002145985368727</guid><pubDate>Wed, 13 May 2009 07:51:00 +0000</pubDate><atom:updated>2009-05-13T00:52:52.947-07:00</atom:updated><title>penryn processors</title><description>&lt;span class=&quot;Apple-style-span&quot; style=&quot;border-collapse: separate; color: rgb(51, 51, 51); font-family: Georgia; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;&quot;&gt;&lt;div class=&quot;post-body entry-content&quot; style=&quot;margin: 0px 0px 0.75em; line-height: 1.6em;&quot;&gt;More details are emerging on Intel&#39;s next-gen Penryn processors, said to benefit greatly in terms of processing power and energy consumption by mixing the Core microarchitecture with the 45nm Hi-k and hafnium metal gate designs.&lt;br /&gt;&lt;br /&gt;This article in Enterprise Networks and Servers, authored by Intel, offers the latest scoop on the six new Penryn designs, plus two new Xeon quads. The company looks like it&#39;s throwing everything but the kitchen sink into these designs, leveraging advanced power management and dynamic acceleration and throwing in streaming video and enhanced instruction set architectures. NewsFactorNetwork reports that Penryn will jam twice as many transistors in 25 percent less space than comparable systems.&lt;br /&gt;&lt;br /&gt;Details on the Nehelem chips, due out in 2008, are included at Enterprise Networks and Servers. Get ready for dynamic management of the cores, threads, cache and interface, as well as simultaneous multi-threading and new SSE4 and ATA instruction set additions.&lt;/div&gt;&lt;div class=&quot;post-footer&quot; style=&quot;margin: 0.75em 0px; color: rgb(153, 153, 153); text-transform: uppercase; letter-spacing: 0.1em; font-family: &#39;Trebuchet MS&#39;,Trebuchet,Arial,Verdana,sans-serif; font-style: normal; font-variant: normal; font-weight: normal; font-size: 78%; font-size-adjust: none; font-stretch: normal; line-height: 1.4em;&quot;&gt;&lt;br /&gt;&lt;/div&gt;&lt;/span&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/penryn-processors.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-5980640735433298741</guid><pubDate>Wed, 13 May 2009 07:49:00 +0000</pubDate><atom:updated>2009-05-13T00:50:33.652-07:00</atom:updated><title>Privacy policy</title><description>&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;Privacy Policy for www.passionprocessor.blogspot.com/&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;If you require any more information or have any questions about our privacy policy, please feel free to contact us by email at&lt;span class=&quot;apple-converted-space&quot;&gt; home50005&lt;/span&gt;@gmail.com.&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;At www.passionprocessor.blogspot.com/, the privacy of our visitors is of extreme importance to us. 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Our advertising partners include&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;b&gt;&lt;span style=&quot;color: black;&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/span&gt;&lt;/b&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;b&gt;&lt;span style=&quot;color: black;&quot;&gt;Google Adsense&lt;/span&gt;&lt;/b&gt;&lt;span style=&quot;color: black;&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;These third-party ad servers or ad networks use technology to the advertisements and links that appear on www.passionprocessor.blogspot.com/ send directly to your browsers. They automatically receive your IP address when this occurs. Other technologies (such as cookies, JavaScript, or Web Beacons) may also be used by the third-party ad networks to measure the effectiveness of their advertisements and / or to personalize the advertising content that you see.&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt; &lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;www.passionprocessor.blogspot.com/ has no access to or control over these cookies that are used by third-party advertisers.&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;b&gt;&lt;span style=&quot;color: black;&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/span&gt;&lt;/b&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;b&gt;&lt;span style=&quot;color: black;&quot;&gt;Internet Based advertising&lt;/span&gt;&lt;/b&gt;&lt;span style=&quot;color: black;&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;Since Google sooner going to display ads based on interests of user that is if you visit sports related websites regularly which have Google adsense ads, you will be grouped as “sport enthusiast” category. This is Internet Advertising approach from Google for this they collect some info which does not include your name, email-id, phone number, address or any such details .You may read about that&lt;span class=&quot;apple-converted-space&quot;&gt; &lt;/span&gt;&lt;/span&gt;&lt;a href=&quot;http://adsense.blogspot.com/2009/03/driving-monetization-with-ads-that.html&quot;&gt;here&lt;/a&gt;&lt;span style=&quot;color: black;&quot;&gt;.&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;You should consult the respective privacy policies of these third-party ad servers for more detailed information on their practices as well as for instructions about how to opt-out of certain practices. www.passionprocessor.blogspot.com/&#39;s privacy policy does not apply to, and we cannot control the activities of, such other advertisers or web sites.&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;If you wish to disable cookies, you may do so through your individual browser options. More detailed information about cookie management with specific web browsers can be found at the browsers&#39; respective websites.&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;  &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color: black;&quot;&gt;&lt;o:p&gt; &lt;/o:p&gt;&lt;/span&gt;&lt;/p&gt;</description><link>http://passionprocessor.blogspot.com/2009/05/privacy-policy.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-8353489746096812597</guid><pubDate>Fri, 10 Apr 2009 17:10:00 +0000</pubDate><atom:updated>2009-04-10T10:11:04.567-07:00</atom:updated><title>Larrabee: Intel’s next generation hybrid CPU / GPU Coming in 2009</title><description>&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(51, 51, 51); font-family: Verdana; font-size: 13px; line-height: 19px; &quot;&gt;&lt;p class=&quot;MsoNormal&quot;&gt;Intel is targeting graphics market with its upcoming Larrabee. Intel claims that the “discrete Larrabee offerings will compete competitively with Radeon and GeForce offerings when it’s finally announced.”&lt;/p&gt;&lt;p class=&quot;MsoNormal&quot;&gt;Larrabee that will be demonstrated at 2008 Spring Intel Developer Forum in &lt;st1:place st=&quot;on&quot;&gt;&lt;st1:city st=&quot;on&quot;&gt;Shanghai&lt;/st1:city&gt;, &lt;st1:country-region st=&quot;on&quot;&gt;China&lt;/st1:country-region&gt;&lt;/st1:place&gt; is a hybrid GPU and CPU based on the x86 instruction set. So, as you see it is more than a GPUand it differs from AMD&#39;s Radeon and NVIDIA&#39;s GeForce processors. And it can also act like a general processor. Larrabee will be able to support OpenGL, DirectX and ray-tracing instructions.&lt;/p&gt;&lt;a href=&quot;http://www.intel.com/pressroom/archive/releases/20080317fact.htm?iid=pr1_releasepri_20080317fact&quot; style=&quot;color: rgb(0, 102, 204); &quot;&gt;Intel&lt;/a&gt; explains “The Larrabee architecture includes a high-performance, wide SIMD vector processing unit (VPU) along with a new set of vector instructions including integer and floating point arithmetic, vector memory operations and conditional instructions. In addition, Larrabee includes a major new hardware coherent cache design enabling the many-core architecture.”&lt;br /&gt;&lt;br /&gt;&lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;font-size: 8pt; &quot;&gt;Read more: &lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;a href=&quot;http://laptopcom.blogspot.com/2008/02/10-important-laptop-and-hardware.html&quot; style=&quot;color: rgb(0, 102, 204); &quot;&gt;&lt;span style=&quot;color: maroon; &quot;&gt;&lt;br /&gt;Intel Core 2 Due T5450 processor &lt;span style=&quot;font-weight: bold; &quot;&gt;VS&lt;/span&gt; Intel Core 2 Due Penryn T9300 in Playing Crysis (Vista) Benchmarks&lt;/span&gt;&lt;/a&gt;&lt;br /&gt;&lt;/p&gt;&lt;span style=&quot;font-size: 12pt; font-family: &#39;Times New Roman&#39;; color: maroon; &quot;&gt;&lt;br /&gt;&lt;/span&gt;&lt;a onblur=&quot;try {parent.deselectBloggerImageGracefully();} catch(e) {}&quot; href=&quot;http://2.bp.blogspot.com/_YetSDlzNM5Q/R-D2E3E80iI/AAAAAAAAAWk/-cDxa07bSiU/s1600-h/Nehalem+processor.jpg&quot; style=&quot;color: rgb(0, 102, 204); &quot;&gt;&lt;img src=&quot;http://2.bp.blogspot.com/_YetSDlzNM5Q/R-D2E3E80iI/AAAAAAAAAWk/-cDxa07bSiU/s320/Nehalem+processor.jpg&quot; alt=&quot;&quot; id=&quot;BLOGGER_PHOTO_ID_5179410134840693282&quot; border=&quot;0&quot; style=&quot;margin-top: 0px; margin-right: auto; margin-bottom: 10px; margin-left: auto; display: block; text-align: center; cursor: pointer; border-width: initial; border-color: initial; padding-top: 6px; padding-right: 6px; padding-bottom: 6px; padding-left: 6px; border-top-width: 1px; border-top-style: solid; border-top-color: rgb(221, 221, 221); border-left-width: 1px; border-left-style: solid; border-left-color: rgb(221, 221, 221); border-bottom-width: 1px; border-bottom-style: solid; border-bottom-color: rgb(192, 192, 192); border-right-width: 1px; border-right-style: solid; border-right-color: rgb(192, 192, 192); &quot; /&gt;&lt;/a&gt;&lt;br /&gt;&lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/p&gt;&lt;b&gt;Larrabee chips&lt;/b&gt; first will ready as separate graphics units in Q4 2008 and will ship in early 2009. After that early next year laptop and desktop-oriented 45nm Nehalem processors with the built-in Larrabee will be released.&lt;br /&gt;&lt;br /&gt;&lt;span&gt;&lt;span style=&quot;font-size: 78%; &quot;&gt;Read more: &lt;/span&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;br /&gt;&lt;span style=&quot;color: maroon; &quot;&gt;&lt;a href=&quot;http://laptopcom.blogspot.com/2008/02/intel-roadmaps-for-this-june-montevina.html&quot; style=&quot;color: rgb(0, 102, 204); &quot;&gt;&lt;span style=&quot;color: maroon; &quot;&gt;Intel Roadmaps for This June: &lt;b&gt;Montevina&lt;/b&gt; Centrino 2 and Centrino 2 vPro platforms&lt;/span&gt;&lt;/a&gt;&lt;br /&gt;&lt;br /&gt;&lt;/span&gt;&lt;p class=&quot;MsoNormal&quot;&gt;&lt;a href=&quot;http://www.intel.com/pressroom/archive/releases/20080317fact.htm?iid=pr1_releasepri_20080317fact&quot; style=&quot;color: rgb(0, 102, 204); &quot;&gt;Nehalem&lt;/a&gt; is a new processor microarchitecture by Intel and it is dynamically scalable with future versions having anywhere from 2 to 8 cores, with Simultaneous Multi-threading, resulting in 4 to 16 thread capability.&lt;/p&gt;&lt;p class=&quot;MsoNormal&quot;&gt;Nehalem will deliver 4 times the memory bandwidth compared to today&#39;s highest-performance Intel Xeon processor-based systems. With up to 8 MB level-3 cache, 731 million transistors, Quickpath interconnects (up to 25.6GB per second), integrated memory controller and optional integrated graphics, Nehalem will eventually scale from notebooks to high-performance servers.&lt;/p&gt;&lt;p class=&quot;MsoNormal&quot;&gt;Other features discussed include support for DDR3-800, 1066, and 1333 memory, SSE4.2 instructions, 32KB instruction cache, 32KB Data Cache, 256K L2 data and instruction low-latency cache per core and new 2-level TLB (Translation Lookaside Buffer) hierarchy.&lt;/p&gt;&lt;p class=&quot;MsoNormal&quot;&gt;&lt;span&gt;&lt;span style=&quot;font-size: 78%; &quot;&gt;Read more: &lt;/span&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/span&gt;&lt;br /&gt;&lt;span style=&quot;color: maroon; &quot;&gt;&lt;a href=&quot;http://laptopcom.blogspot.com/2008/03/13-important-laptop-hardware-and-os.html&quot; style=&quot;color: rgb(0, 102, 204); &quot;&gt;&lt;span style=&quot;color: maroon; &quot;&gt;Intel announces Atom brand for Silverthorne, Menlow&lt;/span&gt;&lt;/a&gt;&lt;/span&gt;&lt;/p&gt;&lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/p&gt;&lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/p&gt;&lt;p class=&quot;MsoNormal&quot;&gt;&lt;a href=&quot;http://www.dailytech.com/Intel%20Discusses%20GPU%20Hybrid%20CPUs/article11088.htm&quot; style=&quot;color: rgb(0, 102, 204); &quot;&gt;&lt;br /&gt;Daily tech&lt;/a&gt; reports:&lt;/p&gt;&lt;p class=&quot;MsoNormal&quot;&gt;Intel’s hybrid CPU and GPU chips are set to be released in two flavors, both of which will be based on the Nehalem CPU architecture. The first version, dubbed Havendale, will be a desktop chip, while the second version, dubbed Auburndale, will be a notebook chip.&lt;/p&gt;&lt;p class=&quot;MsoNormal&quot;&gt;Auburndale and Havendale will have two Nehalem cores paired with a graphics subsystem. The twin cores will share 4MB of L2 cache and feature an integrated dual-channel memory controller that supports memory configurations up to DDR3-1333.”&lt;/p&gt;&lt;p class=&quot;MsoNormal&quot;&gt;&lt;o:p&gt;&lt;/o:p&gt;&lt;/p&gt;&lt;p class=&quot;MsoNormal&quot;&gt;So, in the first and second quarters 2009, we will expect to see 45nm Nehalem processors with the Larrabee and AMD’s Fusion processors, respectively!&lt;/p&gt;&lt;/span&gt;</description><link>http://passionprocessor.blogspot.com/2009/04/larrabee-intels-next-generation-hybrid.html</link><author>noreply@blogger.com (home50005)</author><media:thumbnail xmlns:media="http://search.yahoo.com/mrss/" url="http://2.bp.blogspot.com/_YetSDlzNM5Q/R-D2E3E80iI/AAAAAAAAAWk/-cDxa07bSiU/s72-c/Nehalem+processor.jpg" height="72" width="72"/><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-6384308198092858465</guid><pubDate>Fri, 10 Apr 2009 17:09:00 +0000</pubDate><atom:updated>2009-04-10T10:10:07.166-07:00</atom:updated><title>Pentium® Processors with MMX™ Technology - New Design Options</title><description>&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(185, 185, 185); font-family: &#39;Trebuchet MS&#39;; font-size: 11px; &quot;&gt;Together the Pentium processor with MMX technology and the 430TX PCIset provides developers with flexible new options to create value-added embedded designs and upgrade existing products to new levels of performance. Regardless of which design path a developer may select, the Pentium processor with MMX technology offers performance enhancements that can be especially valuable in today&#39;s most competitive embedded application segments--including &quot;intelligent&quot; POS terminals, telecommunications equipment, networking devices and high-performance industrial computers.&lt;/span&gt;&lt;div&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(185, 185, 185); font-family: &#39;Trebuchet MS&#39;; font-size: 11px;&quot;&gt;&lt;br /&gt;&lt;/span&gt;&lt;/div&gt;&lt;div&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(185, 185, 185); font-family: &#39;Trebuchet MS&#39;; font-size: 11px;&quot;&gt;&lt;br /&gt;&lt;/span&gt;&lt;/div&gt;&lt;div&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(185, 185, 185); font-family: &#39;Trebuchet MS&#39;; font-size: 11px;&quot;&gt;&lt;br /&gt;&lt;/span&gt;&lt;/div&gt;&lt;div&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(185, 185, 185); font-family: &#39;Trebuchet MS&#39;; font-size: 11px;&quot;&gt;&lt;br /&gt;&lt;/span&gt;&lt;/div&gt;&lt;div&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(185, 185, 185); font-family: &#39;Trebuchet MS&#39;; font-size: 11px;&quot;&gt;&lt;br /&gt;&lt;/span&gt;&lt;/div&gt;&lt;div&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(185, 185, 185); font-family: &#39;Trebuchet MS&#39;; font-size: 11px;&quot;&gt;&lt;br /&gt;&lt;/span&gt;&lt;/div&gt;&lt;div&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(185, 185, 185); font-family: &#39;Trebuchet MS&#39;; font-size: 11px;&quot;&gt;&lt;br /&gt;&lt;/span&gt;&lt;/div&gt;&lt;div&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(185, 185, 185); font-family: &#39;Trebuchet MS&#39;; font-size: 11px;&quot;&gt;&lt;br /&gt;&lt;/span&gt;&lt;/div&gt;&lt;div&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(185, 185, 185); font-family: &#39;Trebuchet MS&#39;; font-size: 11px;&quot;&gt;&lt;br /&gt;&lt;/span&gt;&lt;/div&gt;&lt;div&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(185, 185, 185); font-family: &#39;Trebuchet MS&#39;; font-size: 11px;&quot;&gt;&lt;table border=&quot;0&quot; width=&quot;580&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tbody style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td valign=&quot;top&quot; width=&quot;15&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;br /&gt;&lt;/td&gt;&lt;td class=&quot;sectiontext&quot; valign=&quot;top&quot; width=&quot;568&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;table border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tbody style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td class=&quot;sectiontext&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;img src=&quot;http://www.intel.com/design/intarch/pix/mmx2.jpg&quot; alt=&quot;Pentium Processors  - Low Power&quot; align=&quot;right&quot; border=&quot;0&quot; width=&quot;130&quot; height=&quot;80&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot; /&gt;From point-of-sale (POS) terminals and retail kiosks to advanced networking equipment, Pentium® processors with MMX™ technology enable developers of embedded systems to step up to new levels of performance. To make these designs even easier and more flexible, Intel is making the performance advantages of MMX technology available at a choice of integration levels.&lt;/td&gt;&lt;/tr&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td height=&quot;12&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;br /&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;/td&gt;&lt;td style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;img src=&quot;http://www.intel.com/sites/templates/pix/spacer.gif&quot; alt=&quot;&quot; width=&quot;15&quot; height=&quot;1&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot; /&gt;&lt;/td&gt;&lt;td valign=&quot;top&quot; width=&quot;180&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;table border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot; style=&quot;width: 141px; height: 91px; margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tbody style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td bgcolor=&quot;#a6a6a6&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;table border=&quot;0&quot; width=&quot;180&quot; cellpadding=&quot;0&quot; cellspacing=&quot;1&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tbody style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td bgcolor=&quot;#ffffff&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;table border=&quot;0&quot; cellpadding=&quot;8&quot; cellspacing=&quot;0&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tbody style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td class=&quot;boxheader&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;br /&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;/td&gt;&lt;/tr&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td bgcolor=&quot;#e6e6e6&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;table border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tbody style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td colspan=&quot;2&quot; height=&quot;5&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;br /&gt;&lt;/td&gt;&lt;td style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;img src=&quot;http://www.intel.com/design/shared/pix/spacer.gif&quot; alt=&quot;&quot; width=&quot;10&quot; height=&quot;5&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot; /&gt;&lt;/td&gt;&lt;/tr&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td valign=&quot;top&quot; width=&quot;23&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;img src=&quot;http://www.intel.com/sites/templates/pix/boxbullet_gray.gif&quot; alt=&quot;&quot; width=&quot;23&quot; height=&quot;10&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot; /&gt;&lt;/td&gt;&lt;td class=&quot;boxlink&quot; width=&quot;157&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;br /&gt;&lt;/td&gt;&lt;/tr&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td height=&quot;3&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;br /&gt;&lt;/td&gt;&lt;/tr&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td height=&quot;8&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;br /&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;/td&gt;&lt;/tr&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td height=&quot;15&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;br /&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;table border=&quot;0&quot; width=&quot;580&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tbody style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td valign=&quot;top&quot; width=&quot;15&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;img src=&quot;http://www.intel.com/design/shared/pix/spacer.gif&quot; border=&quot;0&quot; width=&quot;16&quot; height=&quot;1&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot; /&gt;&lt;/td&gt;&lt;td class=&quot;sectiontext&quot; valign=&quot;top&quot; width=&quot;568&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;table border=&quot;0&quot; cellpadding=&quot;0&quot; cellspacing=&quot;0&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tbody style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td valign=&quot;top&quot; width=&quot;23&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;img src=&quot;http://www.intel.com/sites/templates/pix/boxbullet_gray.gif&quot; alt=&quot;&quot; width=&quot;23&quot; height=&quot;10&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot; /&gt;&lt;/td&gt;&lt;td class=&quot;sectiontext&quot; width=&quot;545&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;The upgrade path for embedded Intel® architecture includes longer life cycle support for the 200 MHz and 233 MHz Pentium processors with MMX technology.&lt;/td&gt;&lt;/tr&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td valign=&quot;top&quot; width=&quot;23&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;img src=&quot;http://www.intel.com/sites/templates/pix/boxbullet_gray.gif&quot; alt=&quot;&quot; width=&quot;23&quot; height=&quot;10&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot; /&gt;&lt;/td&gt;&lt;td class=&quot;sectiontext&quot; width=&quot;545&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;Intel offers 166 MHz and 266 MHz &lt;a href=&quot;http://www.intel.com/design/intarch/mmx/lpentium.htm&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; color: rgb(138, 200, 0); &quot;&gt;Low-power Pentium processors with MMX technology&lt;/a&gt;. Both are available in thin HL-PBGA packaging, as well as PPGA packaging. The 166 MHz Pentium processor is also available in&lt;a href=&quot;http://www.intel.com/design/intarch/datashts/273232.htm&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; color: rgb(138, 200, 0); &quot;&gt;extended temperature&lt;/a&gt; range -40ºC to +115ºC.&lt;/td&gt;&lt;/tr&gt;&lt;tr style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;td valign=&quot;top&quot; width=&quot;23&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;&lt;img src=&quot;http://www.intel.com/sites/templates/pix/boxbullet_gray.gif&quot; alt=&quot;&quot; width=&quot;23&quot; height=&quot;10&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot; /&gt;&lt;/td&gt;&lt;td class=&quot;sectiontext&quot; width=&quot;545&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 0px; padding-right: 0px; padding-bottom: 0px; padding-left: 0px; &quot;&gt;Also, the Intel 430TX PCIset now supports synchronous DRAM [SDRAM] in embedded applications.&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;/span&gt;&lt;/div&gt;</description><link>http://passionprocessor.blogspot.com/2009/04/pentium-processors-with-mmx-technology.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-5044002243668511922</guid><pubDate>Fri, 10 Apr 2009 17:08:00 +0000</pubDate><atom:updated>2009-04-10T10:09:09.131-07:00</atom:updated><title>AMD Releases Open-Source R600/700 3D Code</title><description>&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(51, 51, 51); font-size: 13px; line-height: 20px; &quot;&gt;The AMD has just released code that will allow for open-source 3D acceleration on their ATI R600 and R700 graphics cards, including all of their newest Radeon HD 4xxx products. This code consists of a demo program that feeds the commands to the hardware, updates to their RadeonHD driver, and a Direct Rendering Manager update. With this code comes working 2D EXA acceleration support for these newer ATI graphics processors as well as basic X-Video support. AMD will be releasing sanitized documentation for these new ATI GPUs in the coming weeks. Phoronix has an article detailing what&#39;s all encompassed by today&#39;s code drop as well as the activities that led to this open-source code coming about for release.&lt;/span&gt;</description><link>http://passionprocessor.blogspot.com/2009/04/amd-releases-open-source-r600700-3d.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item><item><guid isPermaLink="false">tag:blogger.com,1999:blog-4707460742463837792.post-387352854022831080</guid><pubDate>Fri, 10 Apr 2009 17:08:00 +0000</pubDate><atom:updated>2009-04-10T10:08:46.597-07:00</atom:updated><title>Intel Completes Next Generation, 32nm Process Development Phase</title><description>&lt;span class=&quot;Apple-style-span&quot; style=&quot;color: rgb(51, 51, 51); font-size: 13px; &quot;&gt;&lt;div class=&quot;post-body entry-content&quot; style=&quot;margin-top: 0px; margin-right: 0px; margin-bottom: 0.75em; margin-left: 0px; line-height: 1.6em; &quot;&gt;Intel Corporation has completed the development phase of its next-generation manufacturing process that further shrinks chip circuitry to 32 nanometers The company is on track for production readiness of this future generation using even more energy-efficient, denser and higher performing transistors in the fourth quarter of 2009.Intel will provide a multitude of technical details around the 32nm process technology along with several other topics during presentations at the International Electron Devices meeting (IEDM) next week in San Francisco. Finishing the development phase for the company&#39;s 32nm process technology and production readiness in this timeframe means that Intel remains on pace with its ambitious product and manufacturing cadence referred to as the company&#39;s &quot;tick-tock&quot; strategy.That plan revolves around introducing an entirely new processor microarchitecture alternating with a cutting edge manufacturing process about every 12 months, an effort unmatched in the industry. Producing 32nm chips next year would mark the fourth consecutive year Intel has met its goal.The Intel 32nm paper and presentation describe a logic technology that incorporates second-generation high-k + metal gate technology, 193nm immersion lithography for critical patterning layers and enhanced transistor strain techniques. These features enhance the performance and energy efficiency of Intel processors. Intel&#39;s manufacturing process has the highest transistor performance and the highest transistor density of any reported 32nm technology in the industry.&quot;Our manufacturing prowess and resulting products have helped us widen our lead in computing performance and battery life for Intel-based laptops, servers and desktops,&quot; said Mark Bohr, Intel Senior Fellow and director of process architecture and integration. &quot;As we&#39;ve shown this year, the manufacturing strategy and execution have also given us the ability to create entirely new product lines for MIDs, CE equipment, embedded computers and netbooks.&quot;Other Intel IEDM papers will describe a low power system on chip version of Intel&#39;s 45nm process, transistors based on compound semiconductors, substrate engineering to improve performance of 45nm transistors, integrating chemical mechanical polish for the 45nm node and beyond; and, integrating an array of silicon photonics modulators. Intel will also participate in a short course on 22nm CMOS&lt;div style=&quot;clear: both; &quot;&gt;&lt;/div&gt;&lt;/div&gt;&lt;div&gt;&lt;span class=&quot;Apple-style-span&quot; style=&quot;line-height: 20px;&quot;&gt;&lt;br /&gt;&lt;/span&gt;&lt;/div&gt;&lt;div class=&quot;post-footer&quot; style=&quot;margin-top: 0.75em; margin-right: 0px; margin-bottom: 0.75em; margin-left: 0px; color: rgb(153, 153, 153); text-transform: uppercase; letter-spacing: 0.1em; font: normal normal normal 78%/normal &#39;Trebuchet MS&#39;, Trebuchet, Arial, Verdana, sans-serif; line-height: 1.4em; &quot;&gt;&lt;/div&gt;&lt;/span&gt;</description><link>http://passionprocessor.blogspot.com/2009/04/intel-completes-next-generation-32nm.html</link><author>noreply@blogger.com (home50005)</author><thr:total>0</thr:total></item></channel></rss>