tag:blogger.com,1999:blog-28976810588837831042024-03-17T20:02:38.849-07:00Only-VLSIUnknownnoreply@blogger.comBlogger60125tag:blogger.com,1999:blog-2897681058883783104.post-68899585619960150382017-09-16T12:27:00.000-07:002017-09-16T12:27:24.456-07:00Introduction to SystemVerilogSystemVerilog<br />
<br />
SystemVerilog is a combined hardware description language (HDL) and hardware verification language (HVL) based on extensions to Verilog HDL.<br />
<br />
SystemVerilog as a RTL design language is an extension of Verilog HDL containing all features of Verilog. As a verification language SystemVerilog uses object-oriented programming (OOP) techniques similar to that of C++, Java etc. Clearly, the main advantage of SystemVerilog is the unification of HDL and HVL, that provides a single platform for RTL design and verification.<br />
<br />
As a HDL SystemVerilog supports C/C++ like features including typedef, struct, union, enum, etc. These new features can be used for faster and efficient implementation of HDL, increasing the productivity of RTL design process. However, SystemVerilog’s strongest suite comes as a HVL. It provides a complete verification environment supporting constraint random generation, assertion based verification and coverage driven verification.<br />
<br />
Some of the SystemVerilog features include:<br />
<ul>
<li>C type data types int, shortint, etc.</li>
<li>User defined data types using typedef, struct, union, enum</li>
<li>Dynamic data types</li>
<li>Classes for object oriented programming</li>
<li>More operators (like ++, –)</li>
<li>Assertions and coverage.</li>
</ul>
The subsequent chapters in this SystemVerilog tutorial will focus on concepts that are new to SystemVerilog, compared to Verilog. So, it would beneficial to refresh your knowledge of Verilog. <a href="http://only-vlsi.blogspot.com/2007/12/introduction.html">Tutorial on Verilog</a> is already available on Only-VLSI.Unknownnoreply@blogger.com14tag:blogger.com,1999:blog-2897681058883783104.post-36234533302422525772017-09-12T08:33:00.004-07:002017-09-16T12:28:27.641-07:00XMR: Cross Module Reference<div style="text-align: justify;">
Cross Module Reference<span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;">Cross Module Reference abbreviated as XMR is a very useful
concept in Verilog HDL (as well as system Verilog). However it seems to be less
known among many users of Verilog.</span></span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;">XMR is a mechanism built into Verilog to globally </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"><span style="font-family: inherit;"><span style="font-size: 12.0pt;">reference </span></span>(i.e.,
across the modules) to any nets, tasks, functions etc. Using XMR, one
can refer to any object of a module in any other module, irrespective of
whether they are present below or above its hierarchy. Hence, a XMR can be
a: </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></div>
<ul style="text-align: justify;">
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Downward
reference</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> OR</span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Upward
reference</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ul>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;">Consider the following hierarchy:</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></div>
<ul style="text-align: justify;">
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Module
A</span></span><span style="font-family: inherit;"><span style="color: red; font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="color: red; font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="color: red; font-size: 12.0pt;">Net x</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Instance
P of Module B</span></span><span style="font-family: inherit;"><span style="color: orange; font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="color: orange; font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="color: orange; font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="color: orange; font-size: 12.0pt;">Net x</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Instance
M of Module D</span></span><span style="font-family: inherit;"><span style="color: blue; font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="color: blue; font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="color: blue; font-size: 12.0pt;">Net x</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ul>
</ul>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Instance
Q of Module C</span></span><span style="font-family: inherit;"><span style="color: purple; font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="color: purple; font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="color: purple; font-size: 12.0pt;">Net x</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Instance
N of Module E </span></span><span style="font-family: inherit;"><span style="color: #38761d; font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="color: #38761d; font-size: 12.0pt;">Net x</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ul>
</ul>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Instance
R of Module B</span></span><span style="font-family: inherit;"><span style="color: #a64d79; font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="color: #a64d79; font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="color: #a64d79; font-size: 12.0pt;">Net x</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Instance
M of Module D</span></span><span style="font-family: inherit;"><span style="color: yellow; font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="color: yellow; font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="color: yellow; font-size: 12.0pt;">Net x</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ul>
</ul>
</ul>
</ul>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;">In test bench:</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></div>
<ul style="text-align: justify;">
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Instance
top of Module A</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ul>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;">In the above scenario, there is a net named x in all modules. Using XMR each x
can be globally referenced anywhere within the test bench hierarchy as follows.</span></span></div>
<ul style="text-align: justify;">
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;">top.<span style="color: red;">x</span></span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;">top.P.<span style="color: orange;">x</span></span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;">top.P.M.<span style="color: blue;">x</span></span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;"><span style="color: blue;"> </span></span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;">top.Q.<span style="color: purple;">x</span></span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">top.Q.N.<span style="color: #38761d;">x </span></span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;"><span style="color: #38761d;"> </span></span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;">top.R.<span style="color: #a64d79;">x</span></span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;"><span style="color: #a64d79;"> </span></span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;">top.R.M.<span style="color: yellow;">x</span></span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ul>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;">The above references are full path based XMR, all the way
from top. Such a full path name XMR starts with the top module, followed by
each module <b>instance</b> name in the hierarchy, till the enclosing module is
reached. Finally ending with name of the identifier to be referenced. A XMR can
be on either side of an assignment/expression: both left hand side and right
hand side. Writing full path XMRs is quite tedious thankfully Verilog allows both upward and downward references.</span></span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;"><b>Examples of XMRs</b>:</span></span></div>
<ul style="text-align: justify;">
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;">In
Instance P the following XMRs are realized as follows:</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">P.x
refers to net x of Module B in instance P</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">M.x
refers to net x in instance P's instance M of module D</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Q.N.x
refers to net x in instance Q's, instance N of module E</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Here,
as the Q.N.x is not present in downward hierarchy, hence Verilog moves one
step up the hierarchy, and then looks downwards from there. This is an
example of upward reference.</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ul>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Q.x
refers to net x in instance Q of module C</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ul>
</ul>
<ul style="text-align: justify;"><ul><ul>
</ul>
</ul>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">In
Instance R the following XMRs are realized as follows:</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">M.x
refers to net x in instance R's instance of M of module D</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Note:
M.x reference in instances P and R reference to different nets</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ul>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Q.N.x
refers to net x in instance Q's, instance N of module E</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ul>
</ul>
<div style="text-align: justify;">
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<span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"><b>Procedure for resolving XMRs</b>:</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></div>
<ol style="text-align: justify;">
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">First,
search in the current module, then hierarchically downwards from here
(children instances, followed by their children and so on). If found,
resolve it as required XMR.</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Else
then, search one step up in the hierarchy (parent module) and
hierarchically downwards.. If found, resolve it as required XMR.</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Else
repeat step 2, going further one step up in the hierarchy. </span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ol>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;">After following above steps if Verilog is unable to resolve a XMR, it will
result in a compilation error. </span></span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;">In the given hierarchy, in top module M.x will result in resolution error. This is because, M.x can correspond to instance M in either P or R instances, and cannot
be uniquely determined which net to refer. This issue can be resolved by using
either P.M.x or R.M.x.</span></span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;"><b>Uses of XMRs</b>:</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></div>
<ul style="text-align: justify;">
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Extremely
useful in debug and verification.</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<ul>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Can
use XMRs to tap into any signal from anywhere in the entire
design/test-suite</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">Useful
in writing coverpoints for functional coverage</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
<li><span style="font-family: inherit;"><span style="font-size: 12.0pt;">For
debug purpose we can use XMRs to override/force any signals</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></li>
</ul>
</ul>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;">XMRs are one of the unique features that are available in
Verilog (and System Verilog) compared to VHDL.</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;">As noted above, XMRs are not very well known for many, but having
knowledge of XMRs really helps during verification and accelerates debugging.</span></span><span style="font-family: inherit;"><span style="font-size: 12.0pt;"> </span></span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<blockquote class="tr_bq">
<span style="font-family: inherit;"><span style="font-size: 12.0pt;">As a good implementation practice do not use
XMRs in synthesizable RTL. Confine the use of XMRs only to debug/verification, irrespective of
whether they are present in TB or modules themselves (i.e., only to
non-synthesizable code).</span></span></blockquote>
</div>
<span style="font-family: inherit;"><br /></span>
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Unknownnoreply@blogger.com3tag:blogger.com,1999:blog-2897681058883783104.post-63319549052509842552017-09-11T12:57:00.000-07:002017-09-12T06:18:59.571-07:00The new... Only-VLSIHello... <b>Welcome </b>to the new <span style="font-family: "helvetica neue" , "arial" , "helvetica" , sans-serif;">Only-VLSI</span>.<br />
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Thanks.Unknownnoreply@blogger.comtag:blogger.com,1999:blog-2897681058883783104.post-44380792807226875852009-05-31T07:09:00.000-07:002017-09-11T12:50:39.007-07:00Synchronous Reset vs. Asynchronous Reset<span style="font-weight: bold;">Why Reset?</span><br />
<br />
A Reset is required to initialize a hardware design for system operation and to force an ASIC into a known state for simulation.<br />
<br />
A reset simply changes the state of the device/design/ASIC to a user/designer defined state. There are two types of reset, what are they? As you can guess them, they are Synchronous reset and Asynchronous reset.<br />
<br />
<span style="font-weight: bold;">Synchronous Reset</span><br />
<br />
A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the clock. The reset signal is applied as is any other input to the state machine.<br />
<br />
<span style="font-style: italic;">Advantages:</span><br />
<ul>
<li>The advantage to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time.</li>
<li>Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant.</li>
<li>Synchronous resets provide some filtering for the reset signal such that it is not effected by glitches, unless they occur right at the clock edge. A synchronous reset is recommended for some types of designs where the reset is generated by a set of internal conditions. As the clock will filter the logic equation glitches between clock edges.</li>
</ul>
<span style="font-style: italic;">Disadvantages:</span><br />
<ul>
<li>The problem in this topology is with reset assertion. If the reset signal is not long enough to be captured at active clock edge (or the clock may be slow to capture the reset signal), it will result in failure of assertion. In such case the design needs a pulse stretcher to guarantee that a reset pulse is wide enough to be present during the active clock edge.</li>
<li>Another problem with synchronous resets is that the logic synthesis cannot easily distinguish the reset signal from any other data signal. So proper care has to be taken with logic synthesis, else the reset signal may take the fastest path to the flip-flop input there by making worst case timing hard to meet.</li>
<li>In some power saving designs the clocked is gated. In such designed only asynchronous reset will work.</li>
<li>Faster designs that are demanding low data path timing, can not afford to have extra gates and additional net delays in the data path due to logic inserted to handle synchronous resets.</li>
</ul>
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<span style="font-weight: bold;">Asynchronous Reset</span><br />
<br />
An asynchronous reset will affect or reset the state of the flip-flop asynchronously i.e. no matter what the clock signal is. This is considered as high priority signal and system reset happens as soon as the reset assertion is detected.<br />
<br />
<span style="font-style: italic;">Advantages:</span><br />
<ul>
<li>High speeds can be achieved, as the data path is independent of reset signal.</li>
<li>Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present.</li>
<li>As in synchronous reset, no work around is required for logic synthesis.</li>
</ul>
<span style="font-style: italic;">Disadvantages:</span><br />
<ul>
<li>The problem with this type of reset occurs at logic de-assertion rather than at assertion like in synchronous circuits. If the asynchronous reset is released (reset release or reset removal) at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable.</li>
<li>Spurious resets can happen due to reset signal glitches.</li>
</ul>
<span style="font-weight: bold;">Conclusion</span><br />
<br />
Both types of resets have positives and negatives and none of them assure fail-proof design. So there is something called "Asynchronous assertion and Synchronous de-assertion" reset which can be used for best results. (which will be discussed in next post).Unknownnoreply@blogger.com45tag:blogger.com,1999:blog-2897681058883783104.post-76008234784753210382009-05-25T09:31:00.000-07:002009-05-26T01:34:32.093-07:00VLSI Interview Questions with Answers - 11. Why does the present VLSI circuits use MOSFETs instead of BJTs?<br /><a href="javascript:showHide('divVIQ11')">Answer</a><br /><div id="divVIQ11" style="display: none;"><br />Compared to BJTs, MOSFETs can be made very small as they occupy very small silicon area on IC chip and are relatively simple in terms of manufacturing. Moreover digital and memory ICs can be implemented with circuits that use only MOSFETs i.e. no resistors, diodes, etc.<br /></div><br />2. What are the various regions of operation of MOSFET? How are those regions used?<br /><a href="javascript:showHide('divVIQ12')">Answer</a><br /><div id="divVIQ12" style="display: none;"><br />MOSFET has three regions of operation: the cut-off region, the triode region, and the saturation region.<br />The cut-off region and the triode region are used to operate as switch. The saturation region is used to operate as amplifier.<br /></div><br />3. What is threshold voltage?<br /><a href="javascript:showHide('divVIQ13')">Answer</a><br /><div id="divVIQ13" style="display: none;"><br />The value of voltage between Gate and Source i.e. V<sub>GS</sub> at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called threshold voltage (V<sub>t</sub> is positive for NMOS and negative for PMOS).<br /></div><br />4. What does it mean "the channel is pinched off"?<br /><a href="javascript:showHide('divVIQ14')">Answer</a><br /><div id="divVIQ14" style="display: none;"><br />For a MOSFET when V<sub>GS</sub> is greater than V<sub>t</sub>, a channel is induced. As we increase V<sub>DS</sub> current starts flowing from Drain to Source (triode region). When we further increase V<sub>DS</sub>, till the voltage between gate and channel at the drain end to become V<sub>t</sub>, i.e. V<sub>GS</sub> - V<sub>DS</sub> = V<sub>t</sub>, the channel depth at Drain end decreases almost to zero, and the channel is said to be pinched off. This is where a MOSFET enters saturation region.<br /></div><br />5. Explain the three regions of operation of a MOSFET.<br /><a href="javascript:showHide('divVIQ15')">Answer</a><br /><div id="divVIQ15" style="display: none;"><br />Cut-off region: When V<sub>GS</sub> < V<sub>t</sub>, no channel is induced and the MOSFET will be in cut-off region. No current flows.<br />Triode region: When V<sub>GS</sub> ≥ V<sub>t</sub>, a channel will be induced and current starts flowing if V<sub>DS</sub> > 0. MOSFET will be in triode region as long as V<sub>DS</sub> < V<sub>GS</sub> - V<sub>t</sub>.<br />Saturation region: When V<sub>GS</sub> ≥ V<sub>t</sub>, and V<sub>DS</sub> ≥ V<sub>GS</sub> - V<sub>t</sub>, the channel will be in saturation mode, where the current value saturates. There will be little or no effect on MOSFET when V<sub>DS</sub> is further increased.<br /></div><br />6. What is channel-length modulation?<br /><a href="javascript:showHide('divVIQ16')">Answer</a><br /><div id="divVIQ16" style="display: none;"><br />In practice, when V<sub>DS</sub> is further increased beyond saturation point, it does has some effect on the characteristics of the MOSFET. When V<sub>DS</sub> is increased the channel pinch-off point starts moving away from the Drain and towards the Source. Due to which the effective channel length decreases, and this phenomenon is called as Channel Length Modulation.<br /></div><br />7. Explain depletion region.<br /><a href="javascript:showHide('divVIQ17')">Answer</a><br /><div id="divVIQ17" style="display: none;"><br />When a positive voltage is applied across Gate, it causes the free holes (positive charge) to be repelled from the region of substrate under the Gate (the channel region). When these holes are pushed down the substrate they leave behind a carrier-depletion region.<br /></div><br />8. What is body effect?<br /><a href="javascript:showHide('divVIQ18')">Answer</a><br /><div id="divVIQ18" style="display: none;"><br />Usually, in an integrated circuit there will be several MOSFETs and in order to maintain cut-off condition for all MOSFETs the body substrate is connected to the most negative power supply (in case of PMOS most positive power supply). Which causes a reverse bias voltage between source and body that effects the transistor operation, by widening the depletion region. The widened depletion region will result in the reduction of channel depth. To restore the channel depth to its normal depth the VGS has to be increased. This is effectively seen as change in the threshold voltage - V<sub>t</sub>. This effect, which is caused by applying some voltage to body is known as body effect.<br /></div><br />9. Give various factors on which threshold voltage depends.<br /><a href="javascript:showHide('divVIQ19')">Answer</a><br /><div id="divVIQ19" style="display: none;"><br />As discussed in the above question, the V<sub>t</sub> depends on the voltage connected to the Body terminal. It also depends on the temperature, the magnitude of V<sub>t</sub> decreases by about 2mV for every 1<sup>o</sup>C rise in temperature.<br /></div><br />10. Give the Cross-sectional diagram of the CMOS.<br /><a href="javascript:showHide('divVIQ110')">Answer</a><br /><div id="divVIQ110" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjPzl2WtpJDsQ_EkrFr9pu10mkL6TOeVspJrU0AJ0C7bgkf43T2GzntKl_5duz4ekVaoGsLwH9HD3fLRUAUJaWVlv3thFmB-1-R_bPWqrTRLIJ5RXkzGyb6MJCUZE_34mZYmJCUuSCN95j-/s1600-h/f_CMOS_cross_section.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 320px; height: 130px;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjPzl2WtpJDsQ_EkrFr9pu10mkL6TOeVspJrU0AJ0C7bgkf43T2GzntKl_5duz4ekVaoGsLwH9HD3fLRUAUJaWVlv3thFmB-1-R_bPWqrTRLIJ5RXkzGyb6MJCUZE_34mZYmJCUuSCN95j-/s320/f_CMOS_cross_section.jpg" alt="" id="BLOGGER_PHOTO_ID_5339805465900594450" border="0" /></a><br /></div>Unknownnoreply@blogger.com1tag:blogger.com,1999:blog-2897681058883783104.post-64826562902685192142009-02-20T06:20:00.000-08:002009-02-20T06:49:25.099-08:00Type-3: Give Verilog/VHDL code ...Most Common Interview Questions: Type-3: <span style="font-weight: bold;">Give Verilog/VHDL code ...</span><br /><br />The prime intention of the interviewer in asking this question is to see the hands-on experience you have. If you have mentioned that you are familiar with Verilog/VHDL in your resume and attending an ASIC engineer post, then you can expect this question. This question usually comes after asking <a href="http://only-vlsi.blogspot.com/2009/02/type-1-design.html">Type-1</a> and/or <a href="http://only-vlsi.blogspot.com/2009/02/type-2-tell-us-about-designproject-you.html">Type-2</a> questions (explained in previous posts). No interviewer starts with this type of question.<br /><br />The common strategy followed is: initially you will be asked "<a href="http://only-vlsi.blogspot.com/2009/02/type-1-design.html">Type-1: Design a ...</a>" and then as an extension you will be asked to code it in Verilog or VHDL. Further, the interviewer may specifically ask you, to code for synthesis.<br /><br /><span style="font-weight: bold;">Tips</span><br /><ul><li>This question is asked to test your ability to code. <span style="font-style: italic;">Don't ever write a psuedo code or a code with syntax error</span>(s).</li><li>Prepare for this question by coding some basic programs like flip-flops, counters, small FSMs etc. Make sure that you touch most of the commonly used Verilog/VHDL keywords.</li><li>Once you write some code, try to synthesize it and also try to find out the solution(s) if there are any errors.</li><li>Code some combinational and sequential codes. Try to code using hierarchies.</li></ul>This is not a good way of testing one's knowledge, this is usually used to just see the hands-on experience you got. Sometimes this may become crucial if the project (which you are hired for) requires an ASIC design enginner urgently, so if you have enough experience then time can be saved by skipping training.<br /><br /><blockquote><span style="font-style: italic; color: rgb(102, 0, 204);">You might also want to read the following articles</span><br /><br /><a href="http://only-vlsi.blogspot.com/2009/02/type-2-tell-us-about-designproject-you.html"><span style="font-weight: bold;">Type-2: Tell us about a design/project you worked on</span></a><br /><br /><a href="http://only-vlsi.blogspot.com/2009/02/type-1-design.html"><span style="font-weight: bold;">Type-1: Design a ...</span></a><br /><br /><a style="font-weight: bold;" href="http://only-vlsi.blogspot.com/2009/01/first-things-first-preparing-good.html">First Things First -- Preparing a Good Resume</a></blockquote>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-80450730399702078072009-02-11T01:19:00.000-08:002009-02-20T06:22:40.949-08:00Type-2: Tell us about a design/project you worked onMost Common Interview Questions: Type-2: <span style="font-weight: bold;">Tell us about a design/project you worked on<br /></span><br />Prepare for answering this question in any interview you attend, its kind of inevitable. Usually our resumes will be flooded with some projects. So an interviewer, instead of asking about one of those projects, he simply hits the ball into your court by asking this question. In general, interviewers ask to talk about your best work, it could be a design you made out of your interest or a project or part of a coursework. Irrespective of whether interviewer uses the word <span style="font-style: italic;">best</span> its implied that you are going to talk about your best work! Now the ball is in your court you have to give a smart reply using your skills.<br /><br /><span style="font-weight: bold;">How to answer this question?</span><br /><br />Remember that the time you have to answer this is limited. So instead of explaining every aspect of your design in detail, give glimpses of your design. Start taking about the best or challenging part of your design. This is best way of extracting some questions from interview which you can answer with ease. While you are explaining, the interviewer will most probably interrupt you and ask "<span style="color: rgb(255, 0, 0);">why did you use this particular method? why not some other method?</span>". In this case you are expected to give advantages of your design choice has, over other strategies. Failing to answer such questions will result in a very bad impression and ultimately rejection.<br /><br /><span style="font-style: italic;">Example</span>: <span style="color: rgb(255, 0, 0);">Why did you use gray encoding for representing your FSM states? why not one-hot encoding?</span> ... Here you have to know about one-hot encoding and the advantages that gray encoding has w.r.t. your design. If you are smart enough you can say that I considered various encoding techniques and chosen the best suited for my design. Don't forget to justify your statement. On the flip side if you say that I don't know one-hot encoding, the interviewer feels that your knowledge is limited and may also think that you have blindly followed your guides' instructions to use gray encoding.<br /><br /><span style="font-weight: bold;">Why is this question very important?</span><br /><br />You should realize that you are just going to present something you already DID. In other questions you may require some time to think, solve or understand and you may get little tensed if you don't get a proper idea. But nothing like that in this question. As I said above the ball is in court and you should not make an unforced error!<br /><br />All you have to do is use this question as your prime weapon to get the job!<br /><br /><blockquote><span style="font-style: italic; color: rgb(102, 0, 204);">You might also want to read the following articles</span><br /><br /><a href="http://only-vlsi.blogspot.com/2009/02/type-1-design.html"><span style="font-weight: bold;">Type-1: Design a ...</span></a><br /><br /><a style="font-weight: bold;" href="http://only-vlsi.blogspot.com/2009/01/first-things-first-preparing-good.html">First Things First -- Preparing a Good Resume</a></blockquote><br>Unknownnoreply@blogger.com1tag:blogger.com,1999:blog-2897681058883783104.post-82597931518838501062009-02-05T01:45:00.000-08:002009-02-11T01:20:28.771-08:00Type-1: Design a ...Most Common Interview Questions: Type-1: <span style="font-weight: bold;">Design a ...</span><br /><br />This is the most common question one will face in his/her interview, probably the first question which starts testing your knowledge. (I mean this comes after introduction and "Tell us about yourself"). This is a lethal weapon used by the interviewer to test one's abilities: both weak and strong points. The concepts required for solving the problem are generally related to the type of job you are being tested for.<br /><br />The most popular strategy used by the interview in this question is <span style="font-style: italic;">gradual increase in the complexity of the question</span>. It goes like this ... Interviewer states the specifications of the design. You can present as simple/straight forward/redundant answer as possible. The next question could be redesign using only NOR gates or NAND gates. Followed by "what are minimum number of NAND gates required for this particular design" and it goes on.<br /><br />Sometimes it starts with designing a small block. Then you will be asked to embed this module in a bigger picture and analyze the scenario. Where most likely you will face questions like "can the design (you made) be optimized for better performance of the entire module?" or "what drawbacks you see in your design when embedded in the bigger module". Basically tests how good you are with designs with a hierarchy.<br /><br />Another way is step by step removal of assumptions that make the design complex as we go further.<br /><br /><span style="font-weight: bold;">Tips</span><br /><ul><li>Read the job description, think of possible questions or target areas, and prepare for the same.</li><li>ASIC interviews (especially freshers) expect a question dealing timing analysis, synthesis related issues, etc.<br /></li></ul>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-76942811426107835612009-01-26T02:22:00.000-08:002009-02-24T01:08:13.628-08:00First Things First -- Preparing a Good ResumeAs the title says first things first, it’s very important to have good and attractive resume to get an interview call or to get shortlisted. It is always advised to start writing your own resume from scratch instead of copying/following someone else's content or template. So here are some points you should keep in mind before start writing your resume.<br /><ul><li>Most of the times your resume will be first reviewed and shortlisted by HR officers, who rarely have technical knowledge, they just look for some <span style="font-weight: bold; font-style: italic;">keywords </span>provided by the technical manager. Keywords like Verilog, Tools names, years of experience, etc.</li><li>The reviewer usually takes less than 5 minutes (or 3 minutes) to go through your resume, so make it concise.</li><li>Resume should not (or never) be greater than <span style="font-weight: bold;">two pages</span>. Don't try to act smart by using small/tiny font sizes.</li><li>First page should present your best qualities. It’s not like you start low and finish high, in resume you have to always start HIGH.</li><li>Don't make a fancy or colourful resume, keep it strictly professional, use formal fonts like Verdana, Time New Roman, etc. Importantly, maintain proper alignment (not zigzag).</li><li><span style="font-weight: bold;">Contact details</span>: phone number and personal email-id are sufficient. Write them in the first page of the resume - after the name or in the header (top right corner).<br /></li></ul><span style="font-weight: bold;"><br />First Page</span>: Name, Summary, Skills, Work Experience, Education<br /><br /><span style="font-style: italic;">Name</span>: Write your <span style="font-weight: bold;">full name</span>.<br /><br /><span style="font-style: italic;">Summary</span>: First page should present your best qualities. Start with a summary of your profile which should give an idea about your number of years of work experience, the key skills you possess and the type of job you are looking for. Summary is usually 2-3 lines long. Use simple language, no need to be bombastic.<br /><br /><span style="font-style: italic;">Skills</span> include programming languages or HDLs, Technologies known, familiar Tools, etc. If you have a very basic knowledge in something say VHDL, then it is recommended not to mention it. If you think it's really helps to include it then you may write something in brackets like "VHDL (beginner)". I have seen many people writing this: "Operating systems: DOS, Windows 98/2000/XP, Linux", mentioning OS in resume has a wrong understanding by many. It doesn't mean that you used that particular OS, it means that you know "how that particular OS works", like its design, properties, merits, limitations, uses etc. If you just know how to create/delete a file or how to use some commands on OS, then don't mention it.<br /><br /><span style="font-style: italic;">Work Experience</span>: For each company you worked in (including current company), mention your designation, company name, location and period. You can include any internship(s) you did, just say "summer intern" or similar thing as the designation. Always write the list in <span style="font-weight: bold;">chronological order </span>from latest to oldest.<br /><br /><span style="font-style: italic;">Education</span>: Mention two or three latest levels of education you attended like "Masters and Bachelors" or "Masters, Bachelors and Class XII" or etc. As your work experience keeps increasing, the significance of this section keeps coming down. A fresher or less than 2 years experienced candidate will definitely place this section in first page.<br /><br />If you still have some space left, then write about your publications. If you don't have any research papers then start writing about your projects.<br /><br /><span style="font-weight: bold;"><br />Second Page</span>: Projects, Honors/Achievements, Personal information,<br /><br /><span style="font-style: italic;">Projects</span>: List 3-5 best projects you did, in chronological order. Give title, location, period, Technologies used and abstract. Restrict abstract to 4 (or may be 5 if you have space) lines. Don't write everything about the project in resume, so that the interviewer may ask you some questions about it, which by the way should be an advantage. As you expect this scenario, you will prepare and will feel confident and comfortable in the interview. Most likely you will be able to give nice explanation and impress the interviewer.<br /><br /><span style="font-style: italic;">Honors/Achievements</span>: Enumerate all the honors like scholarships, awards, prizes etc.<br /><br /><span style="font-style: italic;">Personal information</span>: Contact information, Languages known, etc.<br /><br />This is a general way of writing a resume, there is no hard and fast rule/template that you should follow the one given above. One always has the liberty to prepare a resume as he/she likes it. <span style="font-style: italic; font-weight: bold;">But once you are done check whether you will shortlist your own resume if you are the person who is reviewing it!</span><br /><br />Last but the not the least, always perform a word to word <span style="font-weight: bold;">spell check </span>manually. Don't trust MS-Word or some other spell check software. Also get it reviewed by your friends and colleagues.Unknownnoreply@blogger.com4tag:blogger.com,1999:blog-2897681058883783104.post-31012962612533250882009-01-20T06:01:00.000-08:002009-01-20T06:07:32.893-08:00Digital Design Interview Questions - All in 11. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)?<br /><a href="javascript:showHide('dd_div1')">Answer</a><br /><div id="dd_div1" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgIQFu3ocTFwA87HPWo48Q7q0pKTW_CS-e2AjmFQYdCQm4RQRPmBfE1nbo08a8qs3bqK2RKsXWp7RLCSrCGV4qQZRxtjJx1dTHvebF-iM2p730gjYYXv1MVcXtUn0C89vbq9jN1PUPXRr1g/s1600-h/xor_buf_inv_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgIQFu3ocTFwA87HPWo48Q7q0pKTW_CS-e2AjmFQYdCQm4RQRPmBfE1nbo08a8qs3bqK2RKsXWp7RLCSrCGV4qQZRxtjJx1dTHvebF-iM2p730gjYYXv1MVcXtUn0C89vbq9jN1PUPXRr1g/s320/xor_buf_inv_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5177241848477294002" border="0" /></a><br /></div><br />2. Implement an 2-input AND gate using a 2x1 mux.<br /><a href="javascript:showHide('dd_div2')">Answer</a><br /><div id="dd_div2" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj-oTTl41FCze81zNsmJi9okbzRDxRrmGgn8zyUs-b8Zz0TneCemz4RvrBLBnL_ljF9v-CZBTtKiKeftX8D_bpRZgPm7Pn3Ui2WYXW6Q1roBQkeOKLqLvAqpWuW_j6uFiWbVfyJWLsE94SA/s1600-h/and_2x1_mux_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj-oTTl41FCze81zNsmJi9okbzRDxRrmGgn8zyUs-b8Zz0TneCemz4RvrBLBnL_ljF9v-CZBTtKiKeftX8D_bpRZgPm7Pn3Ui2WYXW6Q1roBQkeOKLqLvAqpWuW_j6uFiWbVfyJWLsE94SA/s320/and_2x1_mux_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5177242131945135554" border="0" /></a><br /></div><br />3. What is a multiplexer?<br /><a href="javascript:showHide('dd_div3')">Answer</a><br /><div id="dd_div3" style="display: none;"><br />A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output.<br /></div><br />4. What is a ring counter?<br /><a href="javascript:showHide('dd_div4')">Answer</a><br /><div id="dd_div4" style="display: none;"><br />A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on.<br /></div><br />5. Compare and Contrast Synchronous and Asynchronous reset.<br /><a href="javascript:showHide('dd_div5')">Answer</a><br /><div id="dd_div5" style="display: none;"><br />Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset glitches; however, if these glitches occur near the active clock edge, the Flip-flop could go metastable. In some designs, the reset must be generated by a set of internal conditions. A synchronous reset is recommended for these types of designs because it will filter the logic equation glitches between clock.<br />Problem with synchronous resets is that the synthesis tool cannot easily distinguish the reset signal from any other data signal. Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock, if you have a gated clock to save power, the clock may be disabled coincident with the assertion of reset. Only an asynchronous reset will work in this situation, as the reset might be removed prior to the resumption of the clock. Designs that are pushing the limit for data path timing, can not afford to have added gates and additional net delays in the data path due to logic inserted to handle synchronous resets.<br /><br />Asynchronous reset: The major problem with asynchronous resets is the reset release, also called reset removal. Using an asynchronous reset, the designer is guaranteed not to have the reset added to the data path. Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present. Ensure that the release of the reset can occur within one clock period else if the release of the reset occurred on or near a clock edge then flip-flops may go into metastable state.<br /></div><br />6. What is a Johnson counter?<br /><a href="javascript:showHide('dd_div6')">Answer</a><br /><div id="dd_div6" style="display: none;"><br />Johnson counter connects the complement of the output of the last shift register to its input and circulates a stream of ones followed by zeros around the ring. For example, in a 4-register counter, the repeating pattern is: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, so on.<br /></div><br />7. An assembly line has 3 fail safe sensors and one emergency shutdown switch.The line should keep moving unless any of the following conditions arise:<br />(1) If the emergency switch is pressed<br />(2) If the senor1 and sensor2 are activated at the same time.<br />(3) If sensor 2 and sensor3 are activated at the same time.<br />(4) If all the sensors are activated at the same time<br />Suppose a combinational circuit for above case is to be implemented only with NAND Gates. How many minimum number of 2 input NAND gates are required?<br /><a href="javascript:showHide('dd_div7')">Answer</a><br /><div id="dd_div7" style="display: none;"><br />Solve it out!<br /></div><br />8. In a 4-bit Johnson counter How many unused states are present?<br /><a href="javascript:showHide('dd_div8')">Answer</a><br /><div id="dd_div8" style="display: none;"><br />4-bit Johnson counter: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000.<br />8 unused states are present.<br /></div><br />9. Design a 3 input NAND gate using minimum number of 2 input NAND gates.<br /><a href="javascript:showHide('dd_div9')">Answer</a><br /><div id="dd_div9" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgCJBmZ4YagJqrGLlpTt4p3MUE4lYQcBeJXvzg6R3eeMtaeyEzJHNGxWctY_aQZlFTIPjmNbN1USnjuDm5i4N3_BciAhU_5pBUbyPyWiG7mbHcX7wXI-3owLENGH1F_2oPO2q6GcQbbXXK5/s1600-h/3nand_2nand_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgCJBmZ4YagJqrGLlpTt4p3MUE4lYQcBeJXvzg6R3eeMtaeyEzJHNGxWctY_aQZlFTIPjmNbN1USnjuDm5i4N3_BciAhU_5pBUbyPyWiG7mbHcX7wXI-3owLENGH1F_2oPO2q6GcQbbXXK5/s320/3nand_2nand_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5180896315735718530" border="0" /></a><br /></div><br />10. How can you convert a JK flip-flop to a D flip-flop?<br /><a href="javascript:showHide('dd_div10')">Answer</a><br /><div id="dd_div10" style="display: none;"><br />Connect the inverted J input to K input.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgPbe1An2jlrVzq053jxPESmJfv6eHVm2bu5LIPayZVWiwLFhYeqkRr6ZuM9UYmTa-zi7UW4f8eIMFfcWr_Qo7-S6HnWlJ4NLHLH53DwklDWcpOWSYzDPuT1jLlvFa788Wl5Eo7Sunqudqp/s1600-h/jk1_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgPbe1An2jlrVzq053jxPESmJfv6eHVm2bu5LIPayZVWiwLFhYeqkRr6ZuM9UYmTa-zi7UW4f8eIMFfcWr_Qo7-S6HnWlJ4NLHLH53DwklDWcpOWSYzDPuT1jLlvFa788Wl5Eo7Sunqudqp/s320/jk1_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5177242415412977106" border="0" /></a><br /></div><br />11. What are the differences between a flip-flop and a latch?<br /><a href="javascript:showHide('dd_div11')">Answer</a><br /><div id="dd_div11" style="display: none;"><br />Flip-flops are edge-sensitive devices where as latches are level sensitive devices.<br />Flip-flops are immune to glitches where are latches are sensitive to glitches.<br />Latches require less number of gates (and hence less power) than flip-flops.<br />Latches are faster than flip-flops.<br /></div><br />12. What is the difference between Mealy and Moore FSM?<br /><a href="javascript:showHide('dd_div12')">Answer</a><br /><div id="dd_div12" style="display: none;"><br />Mealy FSM uses only input actions, i.e. output depends on input and state. The use of a Mealy FSM leads often to a reduction of the number of states.<br />Moore FSM uses only entry actions, i.e. output depends only on the state. The advantage of the Moore model is a simplification of the behavior.<br /></div><br />13. What are various types of state encoding techniques? Explain them.<br /><a href="javascript:showHide('dd_div13')">Answer</a><br /><div id="dd_div13" style="display: none;"><br /><span style="font-weight: bold;">One-Hot encoding</span>: Each state is represented by a bit flip-flop). If there are four states then it requires four bits (four flip-flops) to represent the current state. The valid state values are 1000, 0100, 0010, and 0001. If the value is 0100, then it means second state is the current state.<br /><br /><span style="font-weight: bold;">One-Cold encoding</span>: Same as one-hot encoding except that '0' is the valid value. If there are four states then it requires four bits (four flip-flops) to represent the current state. The valid state values are 0111, 1011, 1101, and 1110.<br /><br /><span style="font-weight: bold;">Binary encoding</span>: Each state is represented by a binary code. A FSM having '2 power N' states requires only N flip-flops.<br /><br /><span style="font-weight: bold;">Gray encoding</span>: Each state is represented by a Gray code. A FSM having '2 power N' states requires only N flip-flops.<br /></div><br />14. Define Clock Skew , Negative Clock Skew, Positive Clock Skew.<br /><a href="javascript:showHide('dd_div14')">Answer</a><br /><div id="dd_div14" style="display: none;"><br />Clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock.<br />There are two types of clock skew: negative skew and positive skew. Positive skew occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register. Negative skew is the opposite: the receiving register gets the clock earlier than the sending register.<br /></div><br />15. Give the transistor level circuit of a CMOS NAND gate.<br /><a href="javascript:showHide('dd_div15')">Answer</a><br /><div id="dd_div15" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgK9ukNA23mgOsD34tiNIttLLgTrr_OZhmqZpHADojPbO49jO6eeixX0796Cxr0VSsVPianJCdORCOY00TD-bM-t0RhwzktSz4Iup2f1XDG4d1e48tH4u6vw6z3HYRxMfDaFjYpZQjnjvHt/s1600-h/nand_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgK9ukNA23mgOsD34tiNIttLLgTrr_OZhmqZpHADojPbO49jO6eeixX0796Cxr0VSsVPianJCdORCOY00TD-bM-t0RhwzktSz4Iup2f1XDG4d1e48tH4u6vw6z3HYRxMfDaFjYpZQjnjvHt/s320/nand_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5175715700568137122" border="0" /></a><br /></div><br />16. Design a 4-bit comparator circuit.<br /><a href="javascript:showHide('dd_div16')">Answer</a><br /><div id="dd_div16" style="display: none;"><br /><br /></div><br />17. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR (without inverting the output)?<br /><a href="javascript:showHide('dd_div17')">Answer</a><br /><div id="dd_div17" style="display: none;"><br /><br /></div><br />18. Define Metastability.<br /><a href="javascript:showHide('dd_div18')">Answer</a><br /><div id="dd_div18" style="display: none;"><br />If there are setup and hold time violations in any sequential circuit, it enters a state where its output is unpredictable, this state is known as metastable state or quasi stable state, at the end of metastable state, the flip-flop settles down to either logic high or logic low. This whole process is known as metastability.<br /></div><br />19. Compare and contrast between 1's complement and 2's complement notation.<br /><a href="javascript:showHide('dd_div19')">Answer</a><br /><div id="dd_div9" style="display: none;"><br />The only advantage of 1's complement is that it can be calculated easily, just by changing 0's into 1's and 1's into 0's. The 2's complement is calculated in two ways, (i) add 1 to the 1's complement of the number, and (ii) leave all the leading 0s in the least significant positions and keep first 1 unchanged, and then change 0's into 1's and 1's into 0's.<br /><br />The advantages of 2's complement over 1's complement are:<br />(i) For subtraction with complements, 2's complement requires only one addition operation, where as for 1's complement requires two addition operations if there is an end carry.<br />(ii) 1's complement has two arithmetic zeros, all 0's and all 1's.<br /></div><br />20. Give the transistor level circuit of CMOS, nMOS, pMOS, and TTL inverter gate.<br /><a href="javascript:showHide('dd_div20')">Answer</a><br /><div id="dd_div20" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjXJVALFRZaW2JqQsakEyxBHTXJNRq7oB4bOIAZOfuPZTSVTfNvw5k7Z2uWZCQdlJLOjh_eiWuN0dWTeSE-VH_fiovNhJoR-TiOlgLnsZaVpHHN217KOXOmCrhcJ0uC_nkucSsFUyIGfLdq/s1600-h/not_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjXJVALFRZaW2JqQsakEyxBHTXJNRq7oB4bOIAZOfuPZTSVTfNvw5k7Z2uWZCQdlJLOjh_eiWuN0dWTeSE-VH_fiovNhJoR-TiOlgLnsZaVpHHN217KOXOmCrhcJ0uC_nkucSsFUyIGfLdq/s400/not_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5175711774968028562" border="0" /></a><br /></div><br />21. What are set up time and hold time constraints?<br /><a href="javascript:showHide('dd_div21')">Answer</a><br /><div id="dd_div21" style="display: none;"><br />Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.<br />Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.<br />Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable, which is known as as metastable state or quasi stable state. At the end of metastable state, the flip-flop settles down to either logic high or logic low. This whole process is known as metastability.<br /></div><br />22. Give a circuit to divide frequency of clock cycle by two.<br /><a href="javascript:showHide('dd_div22')">Answer</a><br /><div id="dd_div22" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjD3CqUYVLCI_Ta-WokRFemmJOqYzUQus8HbP49zuVLCT7MFdw9EGBOM5e1WAxiyQL-JhKMivNuDzNHd3ej7q71_oVhzF_PHu9ke50ppRTTQwklxDo4F4dIxqjru4Tb8BuQ_UAox_Zfd1jf/s1600-h/divide_2_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjD3CqUYVLCI_Ta-WokRFemmJOqYzUQus8HbP49zuVLCT7MFdw9EGBOM5e1WAxiyQL-JhKMivNuDzNHd3ej7q71_oVhzF_PHu9ke50ppRTTQwklxDo4F4dIxqjru4Tb8BuQ_UAox_Zfd1jf/s320/divide_2_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5177243081132908002" border="0" /></a><br /></div><br />23. Design a divide-by-3 sequential circuit with 50% duty circle.<br /><a href="javascript:showHide('dd_div23')">Answer</a><br /><div id="dd_div23" style="display: none;"><br /><br /></div><br />24. Explain different types of adder circuits.<br /><a href="javascript:showHide('dd_div24')">Answer</a><br /><div id="dd_div24" style="display: none;"><br /><br /></div><br />25. Give two ways of converting a two input NAND gate to an inverter.<br /><a href="javascript:showHide('dd_div25')">Answer</a><br /><div id="dd_div25" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj8NUA17dRtI3yB-ObGM6AeEPDUtV5y1ApovRz6v4xjNfP64Zbflzr6iKNvqCdpqjURBJdLGvvF5FmYXT3-fcPw8EPnavAChL-VPS-nJEcB8fCaECZIK9UEn-XZ8LqXflDdFars5F58Su-m/s1600-h/nand_not2_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj8NUA17dRtI3yB-ObGM6AeEPDUtV5y1ApovRz6v4xjNfP64Zbflzr6iKNvqCdpqjURBJdLGvvF5FmYXT3-fcPw8EPnavAChL-VPS-nJEcB8fCaECZIK9UEn-XZ8LqXflDdFars5F58Su-m/s320/nand_not2_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5180900799681575570" border="0" /></a><br /></div><br />26. Draw a Transmission Gate-based D-Latch.<br /><a href="javascript:showHide('dd_div26')">Answer</a><br /><div id="dd_div26" style="display: none;"><br /><br /></div><br />27. Design a <span class="blsp-spelling-error" id="SPELLING_ERROR_1">FSM</span> which detects the sequence 10101 from a serial line without overlapping.<br /><a href="javascript:showHide('dd_div27')">Answer</a><br /><div id="dd_div27" style="display: none;"><br /><br /></div><br />28. Design a <span class="blsp-spelling-error" id="SPELLING_ERROR_2">FSM</span> which detects the sequence 10101 from a serial line with overlapping.<br /><a href="javascript:showHide('dd_div28')">Answer</a><br /><div id="dd_div28" style="display: none;"><br /><br /></div><br />29. Give the design of 8x1 multiplexer using 2x1 multiplexers.<br /><a href="javascript:showHide('dd_div29')">Answer</a><br /><div id="dd_div29" style="display: none;"><br /><br /></div><br />30. Design a counter which counts from 1 to 10 ( Resets to 1, after 10 ).<br /><a href="javascript:showHide('dd_div30')">Answer</a><br /><div id="dd_div30" style="display: none;"><br /><br /></div><br />31. Design 2 input AND, OR, and EXOR gates using 2 input NAND gate.<br /><a href="javascript:showHide('dd_div31')">Answer</a><br /><div id="dd_div31" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhpk_bvEc4EW7bguYhaLG-bsrE-tAmIItvxjfiT0beDBIacmLxNh_5R0pZ3q1y1OoX2g3ZWz9StiuPyrc_0-TmIIgoN0EDN8SnPwI6lhZa7BpTsW5iwaGnCqW-iGQJx3zfHsDTl3D327NEo/s1600-h/Others_NAND_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhpk_bvEc4EW7bguYhaLG-bsrE-tAmIItvxjfiT0beDBIacmLxNh_5R0pZ3q1y1OoX2g3ZWz9StiuPyrc_0-TmIIgoN0EDN8SnPwI6lhZa7BpTsW5iwaGnCqW-iGQJx3zfHsDTl3D327NEo/s320/Others_NAND_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5180921595913222818" border="0" /></a><br /></div><br />32. Design a circuit which doubles the frequency of a given input clock signal.<br /><a href="javascript:showHide('dd_div32')">Answer</a><br /><div id="dd_div32" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiHrP0jq-xA9iGG4ysI84a8u9xFG9PVnYwAVrE_-Oksw1Zqeqs7aXgla382b5bVIgPG4B0EgN62SmPGV9owMjyO1A6dr_Tzydh18sD84PJo0f91Pbclch6oNCAttfWsR112LtEUmjl4v7lZ/s1600-h/2xfreq_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiHrP0jq-xA9iGG4ysI84a8u9xFG9PVnYwAVrE_-Oksw1Zqeqs7aXgla382b5bVIgPG4B0EgN62SmPGV9owMjyO1A6dr_Tzydh18sD84PJo0f91Pbclch6oNCAttfWsR112LtEUmjl4v7lZ/s320/2xfreq_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5180921922330737346" border="0" /></a><br /></div><br />33. Implement a D-latch using 2x1 multiplexer(s).<br /><a href="javascript:showHide('dd_div33')">Answer</a><br /><div id="dd_div33" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgxRIHY0EeuyIKxWn6unh5Ctqx-_1PJML3YDft1oNRfAHRe8PsfJjXaHT5qQFsUZHDaPuIx39wR91jpAOcqch8UY48SkvolLLAvj5fgMAncfDSjBrNgdsx4kwcPr5nQYctegbYDWx9KgMfS/s1600-h/d_latch_2x1Mux_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgxRIHY0EeuyIKxWn6unh5Ctqx-_1PJML3YDft1oNRfAHRe8PsfJjXaHT5qQFsUZHDaPuIx39wR91jpAOcqch8UY48SkvolLLAvj5fgMAncfDSjBrNgdsx4kwcPr5nQYctegbYDWx9KgMfS/s320/d_latch_2x1Mux_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5180921724762241714" border="0" /></a><br /></div><br />34. Give the excitation table of a JK flip-flop.<br /><a href="javascript:showHide('dd_div34')">Answer</a><br /><div id="dd_div34" style="display: none;"><br /><br /></div><br />35. Give the Binary, Hexadecimal, BCD, and Excess-3 code for decimal 14.<br /><a href="javascript:showHide('dd_div35')">Answer</a><br /><div id="dd_div35" style="display: none;"><br />14:<br />Binary: 1110<br />Hexadecimal: E<br />BCD: 0001 0100<br />Excess-3: 10001<br /></div><br />36. What is race condition?<br /><a href="javascript:showHide('dd_div36')">Answer</a><br /><div id="dd_div36" style="display: none;"><br /><br /></div><br />37. Give 1's and 2's complement of 19.<br /><a href="javascript:showHide('dd_div37')">Answer</a><br /><div id="dd_div37" style="display: none;"><br />19: 10011<br />1's complement: 01100<br />2's complement: 01101<br /></div><br />38. Design a 3:6 decoder.<br /><a href="javascript:showHide('dd_div38')">Answer</a><br /><div id="dd_div38" style="display: none;"><br /><br /></div><br />39. If A*B=C and C*A=B then, what is the Boolean operator * ?<br /><a href="javascript:showHide('dd_div39')">Answer</a><br /><div id="dd_div39" style="display: none;"><br />* is Exclusive-OR.<br /></div><br />40. Design a 3 bit Gray Counter.<br /><a href="javascript:showHide('dd_div40')">Answer</a><br /><div id="dd_div40" style="display: none;"><br /><br /></div><br />41. Expand the following: PLA, PAL, CPLD, FPGA.<br /><a href="javascript:showHide('dd_div41')">Answer</a><br /><div id="dd_div41" style="display: none;"><br />PLA - Programmable Logic Array<br />PAL - Programmable Array Logic<br />CPLD - Complex Programmable Logic Device<br />FPGA - Field-Programmable Gate Array<br /></div><br />42. Implement the functions: X = A'BC + ABC + A'B'C' and Y = ABC + AB'C using a PLA.<br /><a href="javascript:showHide('dd_div42')">Answer</a><br /><div id="dd_div42" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi_RAOgu4OL3n891oWaXb8_TgeyCm_xoNYU5JD8_5leEU1pO13r0vcy6dmrzY-E0E6p5kcRJy6vX_Aj-i0CJn_lsbNroaxq6m4TjYzjtDqVic4qT3rRQNiOzHQ2W52CeoG6-HpU39bFR3UQ/s1600-h/pla_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi_RAOgu4OL3n891oWaXb8_TgeyCm_xoNYU5JD8_5leEU1pO13r0vcy6dmrzY-E0E6p5kcRJy6vX_Aj-i0CJn_lsbNroaxq6m4TjYzjtDqVic4qT3rRQNiOzHQ2W52CeoG6-HpU39bFR3UQ/s400/pla_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5199855656780399714" border="0" /></a><br /></div><br />43. What are PLA and PAL? Give the differences between them.<br /><a href="javascript:showHide('dd_div43')">Answer</a><br /><div id="dd_div43" style="display: none;"><br /> Programmable Logic Array is a programmable device used to implement combinational logic circuits. The PLA has a set of programmable AND planes, which link to a set of programmable OR planes, which can then be conditionally complemented to produce an output.<br /> PAL is programmable array logic, like PLA, it also has a wide, programmable AND plane. Unlike a PLA, the OR plane is fixed, limiting the number of terms that can be ORed together.<br /> Due to fixed OR plane PAL allows extra space, which is used for other basic logic devices, such as multiplexers, exclusive-ORs, and latches. Most importantly, clocked elements, typically flip-flops, could be included in PALs. PALs are also extremely fast.<br /></div><br />44. What is LUT?<br /><a href="javascript:showHide('dd_div44')">Answer</a><br /><div id="dd_div44" style="display: none;"><br />LUT - Look-Up Table. An n-bit look-up table can be implemented with a multiplexer whose select lines are the inputs of the LUT and whose inputs are constants. An n-bit LUT can encode any n-input Boolean function by modeling such functions as truth tables. This is an efficient way of encoding Boolean logic functions, and LUTs with 4-6 bits of input are in fact the key component of modern FPGAs.<br /></div><br />45. What is the significance of FPGAs in modern day electronics? (Applications of FPGA.)<br /><a href="javascript:showHide('dd_div45')">Answer</a><br /><div id="dd_div45" style="display: none;"><br /><ul><li>ASIC prototyping: Due to high cost of ASIC chips, the logic of the application is first verified by dumping HDL code in a FPGA. This helps for faster and cheaper testing. Once the logic is verified then they are made into ASICs.</li><li>Very useful in applications that can make use of the massive parallelism offered by their architecture. Example: code breaking, in particular brute-force attack, of cryptographic algorithms.</li><li>FPGAs are sued for computational kernels such as FFT or Convolution instead of a microprocessor.</li><li>Applications include digital signal processing, software-defined radio, aerospace and defense systems, medical imaging, computer vision, speech recognition, cryptography, bio-informatics, computer hardware emulation and a growing range of other areas.</li></ul><br /></div><br />46. What are the differences between CPLD and FPGA.<br /><a href="javascript:showHide('dd_div46')">Answer</a><br /><div id="dd_div46" style="display: none;"><br /><br /></div><br />47. Compare and contrast FPGA and ASIC digital designing.<br /><a href="javascript:showHide('dd_div47')">Answer</a><br /><div id="dd_div47" style="display: none;"><br /><a href="http://only-vlsi.blogspot.com/2008/05/fpga-vs-asic.html">Click here.</a><br /></div><br />48. Give True or False.<br />(a) CPLD consumes less power per gate when compared to FPGA.<br />(b) CPLD has more complexity than FPGA<br />(c) FPGA design is slower than corresponding ASIC design.<br />(d) FPGA can be used to verify the design before making a ASIC.<br />(e) PALs have programmable OR plane.<br />(f) FPGA designs are cheaper than corresponding ASIC, irrespective of design complexity.<br /><a href="javascript:showHide('dd_div48')">Answer</a><br /><div id="dd_div48" style="display: none;"><br />(a) False<br />(b) False<br />(c) True<br />(d) True<br />(e) False<br />(f) False<br /></div><br />49. Arrange the following in the increasing order of their complexity: FPGA,PLA,CPLD,PAL.<br /><a href="javascript:showHide('dd_div49')">Answer</a><br /><div id="dd_div49" style="display: none;"><br />Increasing order of complexity: PLA, PAL, CPLD, FPGA.<br /></div><br />50. Give the FPGA digital design cycle.<br /><a href="javascript:showHide('dd_div50')">Answer</a><br /><div id="dd_div50" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglbokNbZrSvfNYxCUZCIL1p9fR4R_j8qIPYUYsuqx6CPABmEzT160xk-4ygPooZ_b8dcQEt6wvFNq1Tu_0tDO9TcgP-PCkTYlleJ3f7egpSds1GMvZRNGmrKLGfIZxgyASxoQcCrt2w2Mt/s1600-h/fpga_flow_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglbokNbZrSvfNYxCUZCIL1p9fR4R_j8qIPYUYsuqx6CPABmEzT160xk-4ygPooZ_b8dcQEt6wvFNq1Tu_0tDO9TcgP-PCkTYlleJ3f7egpSds1GMvZRNGmrKLGfIZxgyASxoQcCrt2w2Mt/s400/fpga_flow_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5200583542067922034" border="0" /></a><br /></div><br />51. What is DeMorgan's theorem?<br /><a href="javascript:showHide('dd_div51')">Answer</a><br /><div id="dd_div51" style="display: none;"><br />For N variables, DeMorgan’s theorems are expressed in the following formulas:<br />(ABC..N)' = A' + B' + C' + ... + N' -- The complement of the product is equivalent to the sum of the complements.<br />(A + B + C + ... + N)' = A'B'C'...N' -- The complement of the sum is equivalent to the product of the complements.<br />This relationship so induced is called DeMorgan's duality.<br /></div><br />52. F'(A, B, C, D) = C'D + ABC' + ABCD + D. Express F in Product of Sum form.<br /><a href="javascript:showHide('dd_div52')">Answer</a><br /><div id="dd_div52" style="display: none;"><br />Complementing both sides and applying DeMorgan's Theorem:<br />F(A, B, C, D) = (C + D')(A' + B' + C)(A' + B' + C' + D')(D')<br /></div><br />53. How many squares/cells will be present in the k-map of F(A, B, C)?<br /><a href="javascript:showHide('dd_div53')">Answer</a><br /><div id="dd_div53" style="display: none;"><br />F(A, B, C) has three variables/inputs.<br />Therefore, number of squares/cells in k-map of F = 2<sup>(Number of variables)</sup> = 2<sup>3</sup> = 8.<br /></div><br />54. Simplify F(A, B, C, D) = S ( 0, 1, 4, 5, 7, 8, 9, 12, 13)<br /><a href="javascript:showHide('dd_div54')">Answer</a><br /><div id="dd_div54" style="display: none;"><br />The four variable k-map of the given expression is:<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsooseLy4TYkgNryIO-NI8rDhlrsxU837_Lly8ORFV5KhyphenhyphenamD-SOlR2FMqrO9UoHrnbW0VMYuj7V-nn9HIE4RX1glGz06rRnoNeSiZ0_v-il9bTB8261RUadGO4gp6fN-7XNz3x6US0vE6/s1600-h/boolean_example2_f.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 225px; height: 189px;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsooseLy4TYkgNryIO-NI8rDhlrsxU837_Lly8ORFV5KhyphenhyphenamD-SOlR2FMqrO9UoHrnbW0VMYuj7V-nn9HIE4RX1glGz06rRnoNeSiZ0_v-il9bTB8261RUadGO4gp6fN-7XNz3x6US0vE6/s320/boolean_example2_f.jpg" alt="" id="BLOGGER_PHOTO_ID_5287443744393326802" border="0" /></a><br />The grouping is also shown in the diagram. Hence we get,<br />F(A, B, C, D) = C' + A'BD<br /></div><br />55. Simplify F(A, B, C) = S (0, 2, 4, 5, 6) into Product of Sums.<br /><a href="javascript:showHide('dd_div55')">Answer</a><br /><div id="dd_div55" style="display: none;"><br />The three variable k-map of the given expression is:<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZS13y0JFI-Ykk03kXurJI_XeTyI_R2OigQFQ2IKLXICeMDmVXspZUmZkEvMRXwwPHMZbLjV2q05QD_FOjHLYWEwNC4lxOyxMzu73YqP1a_nJtIGPjbCAhvkd85qtRxnIsvsNduOB80WMp/s1600-h/Boolean_example1_2_f.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 227px; height: 139px;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZS13y0JFI-Ykk03kXurJI_XeTyI_R2OigQFQ2IKLXICeMDmVXspZUmZkEvMRXwwPHMZbLjV2q05QD_FOjHLYWEwNC4lxOyxMzu73YqP1a_nJtIGPjbCAhvkd85qtRxnIsvsNduOB80WMp/s320/Boolean_example1_2_f.jpg" alt="" id="BLOGGER_PHOTO_ID_5287453434431984338" border="0" /></a><br />The 0's are grouped to get the F'.<br />F' = A'C + BC<br /><br />Complementing both sides and using DeMorgan's theorem we get F,<br />F = (A + C')(B' + C')<br /></div><br />56. The simplified expression obtained by using k-map method is unique. True or False. Explain your answer.<br /><a href="javascript:showHide('dd_div56')">Answer</a><br /><div id="dd_div56" style="display: none;"><br />False. The simplest form obtained is not necessarily unique as grouping can be made in different ways.<br /></div><br />57. Give the characteristic tables of RS, JK, D and T flip-flops.<br /><a href="javascript:showHide('dd_div57')">Answer</a><br /><div id="dd_div57" style="display: none;"><br />RS flip-flop.<br /><table><tbody><tr><td>S</td><td>R</td><td>Q(t+1)</td></tr><tr><td>0</td><td>0</td><td>Q(t)</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>?</td></tr></tbody></table><br />JK flip-flop<br /><table><tbody><tr><td>J</td><td>K</td><td>Q(t+1)</td></tr><tr><td>0</td><td>0</td><td>Q(t)</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>Q'(t)</td></tr></tbody></table><br />D flip-flop<br /><table><tbody><tr><td>D</td><td>Q(t+1)</td></tr><tr><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td></tr></tbody></table><br />T flip-flop<br /><table><tbody><tr><td>T</td><td>Q(t+1)</td></tr><tr><td>0</td><td>Q(t)</td></tr><tr><td>1</td><td>Q'(t)</td></tr></tbody></table><br /></div><br />58. Give excitation tables of RS, JK, D and T flip-flops.<br /><a href="javascript:showHide('dd_div58')">Answer</a><br /><div id="dd_div58" style="display: none;"><br />RS flip-flop.<br /><table><tbody><tr><td>Q(t)</td><td>Q(t+1)</td><td>S</td><td>R</td></tr><tr><td>0</td><td>0</td><td>0</td><td>X</td></tr><tr><td>0</td><td>1</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>X</td><td>0</td></tr></tbody></table><br />JK flip-flop<br /><table><tbody><tr><td>Q(t)</td><td>Q(t+1)</td><td>J</td><td>K</td></tr><tr><td>0</td><td>0</td><td>0</td><td>X</td></tr><tr><td>0</td><td>1</td><td>1</td><td>X</td></tr><tr><td>1</td><td>0</td><td>X</td><td>1</td></tr><tr><td>1</td><td>1</td><td>X</td><td>0</td></tr></tbody></table><br />D flip-flop<br /><table><tbody><tr><td>Q(t)</td><td>Q(t+1)</td><td>D</td></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>1</td></tr></tbody></table><br />T flip-flop<br /><table><tbody><tr><td>Q(t)</td><td>Q(t+1)</td><td>T</td></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>0</td></tr></tbody></table><br /></div><br />59. Design a BCD counter with JK flip-flops<br /><a href="javascript:showHide('dd_div59')">Answer</a><br /><div id="dd_div59" style="display: none;"><br /><br /></div><br />60. Design a counter with the following binary sequence 0, 1, 9, 3, 2, 8, 4 and repeat. Use T flip-flops.<br /><a href="javascript:showHide('dd_div60')">Answer</a><br /><div id="dd_div60" style="display: none;"><br /><br /></div>Unknownnoreply@blogger.com223tag:blogger.com,1999:blog-2897681058883783104.post-30729858954061474722009-01-05T10:21:00.000-08:002009-01-05T10:36:34.554-08:00Digital Design Interview Questions - 61. What is DeMorgan's theorem?<br /><a href="javascript:showHide('DD6div1')">Answer</a><br /><div id="DD6div1" style="display: none;"><br />For N variables, DeMorgan’s theorems are expressed in the following formulas:<br />(ABC..N)' = A' + B' + C' + ... + N' -- The complement of the product is equivalent to the sum of the complements.<br />(A + B + C + ... + N)' = A'B'C'...N' -- The complement of the sum is equivalent to the product of the complements.<br />This relationship so induced is called DeMorgan's duality.<br /></div><br />2. F'(A, B, C, D) = C'D + ABC' + ABCD + D. Express F in Product of Sum form.<br /><a href="javascript:showHide('DD6div2')">Answer</a><br /><div id="DD6div2" style="display: none;"><br />Complementing both sides and applying DeMorgan's Theorem:<br />F(A, B, C, D) = (C + D')(A' + B' + C)(A' + B' + C' + D')(D')<br /></div><br />3. How many squares/cells will be present in the k-map of F(A, B, C)?<br /><a href="javascript:showHide('DD6div3')">Answer</a><br /><div id="DD6div3" style="display: none;"><br />F(A, B, C) has three variables/inputs.<br />Therefore, number of squares/cells in k-map of F = 2<sup>(Number of variables)</sup> = 2<sup>3</sup> = 8.<br /></div><br />4. Simplify F(A, B, C, D) = Σ ( 0, 1, 4, 5, 7, 8, 9, 12, 13)<br /><a href="javascript:showHide('DD6div4')">Answer</a><br /><div id="DD6div4" style="display: none;"><br />The four variable k-map of the given expression is:<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsooseLy4TYkgNryIO-NI8rDhlrsxU837_Lly8ORFV5KhyphenhyphenamD-SOlR2FMqrO9UoHrnbW0VMYuj7V-nn9HIE4RX1glGz06rRnoNeSiZ0_v-il9bTB8261RUadGO4gp6fN-7XNz3x6US0vE6/s1600-h/boolean_example2_f.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 225px; height: 189px;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsooseLy4TYkgNryIO-NI8rDhlrsxU837_Lly8ORFV5KhyphenhyphenamD-SOlR2FMqrO9UoHrnbW0VMYuj7V-nn9HIE4RX1glGz06rRnoNeSiZ0_v-il9bTB8261RUadGO4gp6fN-7XNz3x6US0vE6/s320/boolean_example2_f.jpg" alt="" id="BLOGGER_PHOTO_ID_5287443744393326802" border="0" /></a><br />The grouping is also shown in the diagram. Hence we get,<br />F(A, B, C, D) = C' + A'BD<br /></div><br />5. Simplify F(A, B, C) = Σ (0, 2, 4, 5, 6) into Product of Sums.<br /><a href="javascript:showHide('DD6div5')">Answer</a><br /><div id="DD6div5" style="display: none;"><br />The three variable k-map of the given expression is:<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZS13y0JFI-Ykk03kXurJI_XeTyI_R2OigQFQ2IKLXICeMDmVXspZUmZkEvMRXwwPHMZbLjV2q05QD_FOjHLYWEwNC4lxOyxMzu73YqP1a_nJtIGPjbCAhvkd85qtRxnIsvsNduOB80WMp/s1600-h/Boolean_example1_2_f.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 227px; height: 139px;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZS13y0JFI-Ykk03kXurJI_XeTyI_R2OigQFQ2IKLXICeMDmVXspZUmZkEvMRXwwPHMZbLjV2q05QD_FOjHLYWEwNC4lxOyxMzu73YqP1a_nJtIGPjbCAhvkd85qtRxnIsvsNduOB80WMp/s320/Boolean_example1_2_f.jpg" alt="" id="BLOGGER_PHOTO_ID_5287453434431984338" border="0" /></a><br />The 0's are grouped to get the F'.<br />F' = A'C + BC<br /><br />Complementing both sides and using DeMorgan's theorem we get F,<br />F = (A + C')(B' + C')<br /></div><br />6. The simplified expression obtained by using k-map method is unique. True or False. Explain your answer.<br /><a href="javascript:showHide('DD6div6')">Answer</a><br /><div id="DD6div6" style="display: none;"><br />False. The simplest form obtained is not necessarily unique as grouping can be made in different ways.<br /></div><br />7. Give the characteristic tables of RS, JK, D and T flip-flops.<br /><a href="javascript:showHide('DD6div7')">Answer</a><br /><div id="DD6div7" style="display: none;"><br />RS flip-flop.<br /><table><tbody><tr><td>S</td><td>R</td><td>Q(t+1)</td></tr><tr><td>0</td><td>0</td><td>Q(t)</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>?</td></tr></tbody></table><br />JK flip-flop<br /><table><tbody><tr><td>J</td><td>K</td><td>Q(t+1)</td></tr><tr><td>0</td><td>0</td><td>Q(t)</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>Q'(t)</td></tr></tbody></table><br />D flip-flop<br /><table><tbody><tr><td>D</td><td>Q(t+1)</td></tr><tr><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td></tr></tbody></table><br />T flip-flop<br /><table><tbody><tr><td>T</td><td>Q(t+1)</td></tr><tr><td>0</td><td>Q(t)</td></tr><tr><td>1</td><td>Q'(t)</td></tr></tbody></table><br /></div><br />8. Give excitation tables of RS, JK, D and T flip-flops.<br /><a href="javascript:showHide('DD6div8')">Answer</a><br /><div id="DD6div8" style="display: none;"><br />RS flip-flop.<br /><table><tbody><tr><td>Q(t)</td><td>Q(t+1)</td><td>S</td><td>R</td></tr><tr><td>0</td><td>0</td><td>0</td><td>X</td></tr><tr><td>0</td><td>1</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>X</td><td>0</td></tr></tbody></table><br />JK flip-flop<br /><table><tbody><tr><td>Q(t)</td><td>Q(t+1)</td><td>J</td><td>K</td></tr><tr><td>0</td><td>0</td><td>0</td><td>X</td></tr><tr><td>0</td><td>1</td><td>1</td><td>X</td></tr><tr><td>1</td><td>0</td><td>X</td><td>1</td></tr><tr><td>1</td><td>1</td><td>X</td><td>0</td></tr></tbody></table><br />D flip-flop<br /><table><tbody><tr><td>Q(t)</td><td>Q(t+1)</td><td>D</td></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>1</td></tr></tbody></table><br />T flip-flop<br /><table><tbody><tr><td>Q(t)</td><td>Q(t+1)</td><td>T</td></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>1</td><td>1</td><td>0</td></tr></tbody></table><br /></div><br />9. Design a BCD counter with JK flip-flops<br /><a href="javascript:showHide('DD6div9')">Answer</a><br /><div id="DD6div9" style="display: none;"><br /><br /></div><br />10. Design a counter with the following binary sequence 0, 1, 9, 3, 2, 8, 4 and repeat. Use T flip-flops.<br /><a href="javascript:showHide('DD6div10')">Answer</a><br /><div id="DD6div10" style="display: none;"><br /><br /></div>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-70661458048795065292009-01-04T04:18:00.000-08:002009-05-31T07:11:25.816-07:00Boolean Expression Simplification<span style="font-weight: bold;">The k-map Method</span><br /><br />The "Karnaugh Map Method", also known as k-map method, is popularly used to simplify Boolean expressions. The map method is first proposed by Veitch and then modified by Karnaugh, hence it is also known as "Veitch Diagram". The map is a diagram made up of squares (equal to 2 power number of inputs/variables). Each square represents a minterm, hence any Boolean expression can be represented graphically using a k-map.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhGvpvG-q3LUc8QyqyUE5sDwzNCg_xKDqJ745pCnoGwKJAwFq4xWXOSd94vS9mUA6rCbMA39wClHRBWTeClgmr-uH7ek_7inC5XuC1LT4wrApLpwi3p7T9LLYYIruUkW_UrPkvKa9G1YmJH/s1600-h/Boolean1_f.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 160px; height: 320px;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhGvpvG-q3LUc8QyqyUE5sDwzNCg_xKDqJ745pCnoGwKJAwFq4xWXOSd94vS9mUA6rCbMA39wClHRBWTeClgmr-uH7ek_7inC5XuC1LT4wrApLpwi3p7T9LLYYIruUkW_UrPkvKa9G1YmJH/s320/Boolean1_f.jpg" alt="" id="BLOGGER_PHOTO_ID_5287443575640016082" border="0" /></a><br />The above diagram shows two (I), three (II) and four (III) variable k-maps. The number of squares is equal 2 power number of variables. Two adjacent squares will differ only by one variable. The numbers inside the squares are shown for understanding purpose only. The number shown corresponds to a minterm in the the Boolean expression.<br /><br /><span style="font-weight: bold;">Simplification using k-map</span>:<br /><ul><li>Obtain the logic expression in canonical form.</li><li>Identify all the minterms that produce an output of logic level 1 and place 1 in appropriate k-map cell/square. All others cells must contain a 0.</li><li> Every square containing 1 must be considered at least once.</li><li> A square containing 1 can be included in as many groups as desired.</li><li>There can be isolated 1's, i.e. which cannot be included in any group.</li><li> A group must be as large as possible. The number of squares in a group must be a power of 2 i.e. 2, 4, 8, ... so on.<br /></li><li>The map is considered to be folded or spherical, therefore squares at the end of a row or column are treated as adjacent squares.<br /></li></ul>The simplest Boolean expression contains minimum number of literals in any one in sum of products or products of sum. The simplest form obtained is not necessarily unique as grouping can be made in different ways.<br /><br /><span style="font-weight: bold;">Valid Groups</span><br /><br />The following diagram illustrates the valid grouping k-map method.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZKQYOfHusg0v8KJgpH4s40BoOO7ha-c1t17im1XQBIkOxDQPrkEtC85ek3BTLSTsJGNey4KcG_0owMy7BWRZ4HF_nNnlKyZmEiaN-a1RYPD2fr9xQre0Tetp906XX5gGWn74vSuOwvgoG/s1600-h/Boolean_grouping_f.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 400px; height: 313px;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZKQYOfHusg0v8KJgpH4s40BoOO7ha-c1t17im1XQBIkOxDQPrkEtC85ek3BTLSTsJGNey4KcG_0owMy7BWRZ4HF_nNnlKyZmEiaN-a1RYPD2fr9xQre0Tetp906XX5gGWn74vSuOwvgoG/s400/Boolean_grouping_f.jpg" alt="" id="BLOGGER_PHOTO_ID_5287444947070859202" border="0" /></a><br /><span style="font-weight: bold;">Simplification: Product of Sums</span><br /><br />The above method gives a simplified expression in Sum of Products form. With slight modification to the above method, we can get the simplified expression in Product of Sums form. Group adjacent 0's instead of 1's, which gives us the complement of the function i.e. F'. The complement of obtained F' gives us the required expression F, which is done using the DeMorgan's theorem. See <a href="http://only-vlsi.blogspot.com/2009/01/boolean-expression-simplification.html#ex2">Example-2</a> below for better understanding.<br /><br /><span style="font-weight: bold;">Examples</span>:<br /><br /><span style="color: rgb(102, 0, 204);">1. Simplify F(A, B, C) = Σ (0, 2, 4, 5, 6).</span><br /><br />The three variable k-map of the given expression is:<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiEKsDg5ooHnwjfsji_ekQxxaKHG63qF-kFwxrvI9ohQlzBeWiJXASEKeO06ZVdhDBPlBRB7uKlHzxgHhIG9zuSJEEzvB6rjI_bFVrJpCxHaYmI_Gu8XgwkOzTtDpg6OF6RDjZjYg-LNK7a/s1600-h/Boolean_example1_f.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 227px; height: 138px;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiEKsDg5ooHnwjfsji_ekQxxaKHG63qF-kFwxrvI9ohQlzBeWiJXASEKeO06ZVdhDBPlBRB7uKlHzxgHhIG9zuSJEEzvB6rjI_bFVrJpCxHaYmI_Gu8XgwkOzTtDpg6OF6RDjZjYg-LNK7a/s320/Boolean_example1_f.jpg" alt="" id="BLOGGER_PHOTO_ID_5287443665942245570" border="0" /></a><br />The grouping is also shown in the diagram. Hence we get,<br />F(A, B, C) = AB' + C'<br /><span style="color: rgb(102, 0, 204);"><br /><br /></span><span style="color: rgb(102, 0, 204);"><a name="ex2"></a>2. Simplify F(A, B, C) = Σ (0, 2, 4, 5, 6) into Product of Sums.</span><br /><br />The three variable k-map of the given expression is:<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZS13y0JFI-Ykk03kXurJI_XeTyI_R2OigQFQ2IKLXICeMDmVXspZUmZkEvMRXwwPHMZbLjV2q05QD_FOjHLYWEwNC4lxOyxMzu73YqP1a_nJtIGPjbCAhvkd85qtRxnIsvsNduOB80WMp/s1600-h/Boolean_example1_2_f.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 227px; height: 139px;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZS13y0JFI-Ykk03kXurJI_XeTyI_R2OigQFQ2IKLXICeMDmVXspZUmZkEvMRXwwPHMZbLjV2q05QD_FOjHLYWEwNC4lxOyxMzu73YqP1a_nJtIGPjbCAhvkd85qtRxnIsvsNduOB80WMp/s320/Boolean_example1_2_f.jpg" alt="" id="BLOGGER_PHOTO_ID_5287453434431984338" border="0" /></a><br />The 0's are grouped to get the F'.<br />F' = A'C + BC<br /><br />Complementing both sides and using DeMorgan's theorem we get F,<br />F = (A + C')(B' + C')<br /><span style="color: rgb(102, 0, 204);"><br /><br />3. Simplify F(A, B, C, D) = Σ( 0, 1, 4, 5, 7, 8, 9, 12, 13)</span><br /><br />The four variable k-map of the given expression is:<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsooseLy4TYkgNryIO-NI8rDhlrsxU837_Lly8ORFV5KhyphenhyphenamD-SOlR2FMqrO9UoHrnbW0VMYuj7V-nn9HIE4RX1glGz06rRnoNeSiZ0_v-il9bTB8261RUadGO4gp6fN-7XNz3x6US0vE6/s1600-h/boolean_example2_f.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 225px; height: 189px;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsooseLy4TYkgNryIO-NI8rDhlrsxU837_Lly8ORFV5KhyphenhyphenamD-SOlR2FMqrO9UoHrnbW0VMYuj7V-nn9HIE4RX1glGz06rRnoNeSiZ0_v-il9bTB8261RUadGO4gp6fN-7XNz3x6US0vE6/s320/boolean_example2_f.jpg" alt="" id="BLOGGER_PHOTO_ID_5287443744393326802" border="0" /></a><br />The grouping is also shown in the diagram. Hence we get,<br />F(A, B, C, D) = C' + A'BDUnknownnoreply@blogger.com1tag:blogger.com,1999:blog-2897681058883783104.post-72243151240376975562008-06-10T06:57:00.000-07:002009-05-31T07:11:25.816-07:00Finite State Machine<span style="font-weight: bold;">Definition</span><br /><br />A machine consisting of a set of states, a start state, an input, and a transition function that maps input and current states to a next state. Machine begins in the start state with an input. It changes to new states depending on the transition function. The transition function depends on current states and inputs. The output of the machine depends on input and/or current state.<br /><br />There are two types of FSMs which are popularly used in the digital design. They are<br /><ul><li>Moore machine</li><li>Mealy machine<br /></li></ul><span style="font-weight: bold;">Moore machine</span><br /><br />In Moore machine the output depends only on current state.The advantage of the Moore model is a simplification of the behavior.<br /><br /><span style="font-weight: bold;">Mealy machine</span><br /><br />In Mealy machine the output depend on both current state and input.The advantage of the Mealy model is that it may lead to reduction of the number of states.<br /><br />In both models the next state depends on current state and input. Some times designers use mixed models. States will be encoded for representing a particular state.<br /><br /><span style="font-weight: bold;">Representation of a FSM</span><br /><br />A FSM can be represented in two forms:<br /><ul><li>Graph Notation</li><li>State Transition Table<br /></li></ul><span style="font-weight: bold;">Graph Notation</span><br /><ul><li>In this representation every state is a node. A node is represented using a circular shape and the state code is written within the circular shape.</li><li>The state transitions are represented by an edge with arrow head. The tail of the edge shows current state and arrow points to next state, depending on the input and current state. The state transition condition is written on the edge.</li><li>The initial/start state is sometime represented by a double lined circular shape, or a different colour shade.</li></ul>The following image shows the way of graph notation of FSM. The codes <span style="font-style: italic;">00</span> and <span style="font-style: italic;">11</span> are the state codes. <span style="font-style: italic;">00</span> is the value of initial/starting/reset state. The machine will start with <span style="font-style: italic;">00</span> state. If the machine is reseted then the next state will be <span style="font-style: italic;">00</span> state.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh7sysxhcM5oyHSnqRp1V_J5SrMFULu51fJPIIIP7XRHIauH4I58c5avf77Ko5fRldMIke7xEBejO-5xpV9cm1ivN7uQNQhLm3Lw7qkgc6OuEWVQHaPkRc3NzKOleQ0JqEdyKVkfAl5uAWw/s1600-h/fsm1_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh7sysxhcM5oyHSnqRp1V_J5SrMFULu51fJPIIIP7XRHIauH4I58c5avf77Ko5fRldMIke7xEBejO-5xpV9cm1ivN7uQNQhLm3Lw7qkgc6OuEWVQHaPkRc3NzKOleQ0JqEdyKVkfAl5uAWw/s400/fsm1_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5210253946541027442" border="0" /></a><br /><span style="font-weight: bold;">State Transition Table</span><br /><br />The State Transition Table has the following columns:<br /><ul><li>Current State: Contains current state code</li><li>Input: Input values of the FSM</li><li>Next State: Contains the next state code</li><li>Output: Expected output values<br /></li></ul>An example of state transition table is shown below.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgmb5F_bjRkdupHcMb-i0C5TWdnEFcOSvZ68d1ia46fSLLdPSwQoIAp_WLjUNE1I_rV3nVUATO4ouwLDDxmnzbtGDY3I6yLAHrngyv_cqZt8ytqTSTCCQEB9-cijr308rxyjOAXwddI7DCr/s1600-h/fsm2_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgmb5F_bjRkdupHcMb-i0C5TWdnEFcOSvZ68d1ia46fSLLdPSwQoIAp_WLjUNE1I_rV3nVUATO4ouwLDDxmnzbtGDY3I6yLAHrngyv_cqZt8ytqTSTCCQEB9-cijr308rxyjOAXwddI7DCr/s400/fsm2_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5210254228439163170" border="0" /></a><br /><span style="font-weight: bold;">Mealy FSM</span><br /><br />In Mealy machine the output depend on both current state and input.The advantage of the Mealy model is that it may lead to reduction of the number of states.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgQqXC2MMMuA0qif_rgG3rcPghTj08GImgh-j4bCSps2vA2x3SoxSf0btqWBO5EwRDy8RiPpaRCQ1OSQFgZrm9rWmNX06GaJvydax30QCjcx69gMsgwWHJxs407v2Xw9hswqB7jRsvavJTW/s1600-h/fsm1_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgQqXC2MMMuA0qif_rgG3rcPghTj08GImgh-j4bCSps2vA2x3SoxSf0btqWBO5EwRDy8RiPpaRCQ1OSQFgZrm9rWmNX06GaJvydax30QCjcx69gMsgwWHJxs407v2Xw9hswqB7jRsvavJTW/s400/fsm1_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5211041074752148178" border="0" /></a><br />The block diagram of the Mealy FSM is shown above. The output function depends on input also. The current state function updates the current state register (number of bits depends on state encoding used).<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjbqNhlujmKBkAf4Df8DCMhzbLyuq73C5xRp-aGUqTon1NeA2QYXlB9pYP8Aq6sQsxCbdOWyQvxgMutUrsSn3g7VZA1DahpHAC5cRxmAxxQWGFWZnMXGBAlp5b4NDpWsbsQHaPJyiobDAXy/s1600-h/mealy_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjbqNhlujmKBkAf4Df8DCMhzbLyuq73C5xRp-aGUqTon1NeA2QYXlB9pYP8Aq6sQsxCbdOWyQvxgMutUrsSn3g7VZA1DahpHAC5cRxmAxxQWGFWZnMXGBAlp5b4NDpWsbsQHaPJyiobDAXy/s320/mealy_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5211048292289171058" border="0" /></a><br />The above FSM shows an example of a Mealy FSM, the text on the arrow lines show (condition)/(output). '<span style="font-style: italic;">a</span>' is the input and '<span style="font-style: italic;">x</span>' is the output.<br /><br /><span style="font-weight: bold;">Moore FSM</span><br /><br />In Moore machine the output depends only on current state.The advantage of the Moore model is a simplification of the behavior.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjRsIYdd36bbVDOYR_XYPoZZ1lHzP8FEzWwWD0nQczl6ud5sIO7N33qrdbIWLJ31fR-PdiFPkT5-RiIpUQ__avavXmTssRfgLFaQN61Sgci7CVBorJjguOPqvcnzauIMW7Mw8skZpBYsxrG/s1600-h/fsm2_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjRsIYdd36bbVDOYR_XYPoZZ1lHzP8FEzWwWD0nQczl6ud5sIO7N33qrdbIWLJ31fR-PdiFPkT5-RiIpUQ__avavXmTssRfgLFaQN61Sgci7CVBorJjguOPqvcnzauIMW7Mw8skZpBYsxrG/s400/fsm2_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5211041079550377538" border="0" /></a><br />The above figure shows the block diagram of a Moore FSM. The output function doesn't depend on input. The current state function updates the current state register.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiZW6gxPstmRlqO59Cew0piyynyj9fEhkZRpKovrXx5lGDKWAj9ECoau24Szs4v3avYdAixoMZEEHmdoe9EE86HdN-9TsV13Q3tkz5RPegN0c0v2ryNPO1Wttp-hSIWVaxk6tV8e8EyCiAJ/s1600-h/moore_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiZW6gxPstmRlqO59Cew0piyynyj9fEhkZRpKovrXx5lGDKWAj9ECoau24Szs4v3avYdAixoMZEEHmdoe9EE86HdN-9TsV13Q3tkz5RPegN0c0v2ryNPO1Wttp-hSIWVaxk6tV8e8EyCiAJ/s320/moore_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5211048340348387650" border="0" /></a><br />The above FSM shows an example of a Moore FSM. '<span style="font-style: italic;">a</span>' is the input. Inside every circle the text is (State code)/(output). Here there is only one output, in state '<span style="font-style: italic;">11</span>' the output is '<span style="font-style: italic;">1</span>'.<br /><br />In both the FSMs the reset signal will change the contents of current state register to initial/reset state.<br /><br /><span style="font-weight: bold;">State Encoding</span><br /><br />In a FSM design each state is represented by a binary code, which are used to identify the state of the machine. These codes are the possible values of the state register. The process of assigning the binary codes to each state is known as state encoding.<br />The choice of encoding plays a key role in the FSM design. It influences the complexity, size, power consumption, speed of the design. If the encoding is such that the transitions of flip-flops (of state register) are minimized then the power will be saved. The timing of the machine are often affected by the choice of encoding.<br />The choice of encoding depends on the type of technology used like ASIC, FPGA, CPLD etc. and also the design specifications.<br /><br /><span style="font-weight: bold;">State encoding techniques</span><br /><br />The following are the most common state encoding techniques used.<br /><ul><li>Binary encoding</li><li>One-hot encoding</li><li>Gray encoding<br /></li></ul>In the following explanation assume that there are <span style="font-style: italic;">N</span> number of states in the FSM.<br /><span style="font-weight: bold;"><br />Binary encoding</span><br />The code of a state is simply a binary number. The number of bits is equal to log<sub>2</sub>(N) rounded to next natural number. Suppose <span style="font-style: italic;">N = 6</span>, then the number of bits are 3, and the state codes are:<br />S0 - 000<br />S1 - 001<br />S2 - 010<br />S3 - 011<br />S4 - 100<br />S5 - 101<br /><br /><span style="font-weight: bold;">One-hot encoding</span><br />In one-hot encoding only one bit of the state vector is asserted for any given state. All other state bits are zero. Thus if there are <span style="font-style: italic;">N</span> states then <span style="font-style: italic;">N</span> state flip-flops are required. As only one bit remains logic high and rest are logic low, it is called as One-hot encoding. If <span style="font-style: italic;">N = 5</span>, then the number of bits (flip-flops) required are 5, and the state codes are:<br />S0 - 00001<br />S1 - 00010<br />S2 - 00100<br />S3 - 01000<br />S4 - 10000<br /><br />To know more about one-hot encoding click <a href="http://only-vlsi.blogspot.com/2008/06/one-hot-encoding.html">here</a>.<br /><br /><span style="font-weight: bold;">Gray encoding</span><br />Gray encoding uses the Gray codes, also known as reflected binary codes, to represent states, where two successive codes differ in only one digit. This helps is reducing the number of transition of the flip-flops outputs. The number of bits is equal to log<sub>2</sub>(N) rounded to next natural number. If N = 4, then 2 flip-flops are required and the state codes are:<br />S0 - 00<br />S1 - 01<br />S2 - 11<br />S3 - 10<br /><br />Designing a FSM is the most common and challenging task for every digital logic designer. One of the key factors for optimizing a FSM design is the choice of state coding, which influences the complexity of the logic functions, the hardware costs of the circuits, timing issues, power usage, etc. There are several options like binary encoding, gray encoding, one-hot encoding, etc. The choice of the designer depends on the factors like technology, design specifications, etc.<span style="font-weight: bold;"><br /></span>Unknownnoreply@blogger.com1tag:blogger.com,1999:blog-2897681058883783104.post-53781414897004156512008-06-09T03:29:00.000-07:002009-01-20T05:08:21.975-08:00One-hot EncodingDesigning a FSM is the most common and challenging task for every digital logic designer. One of the key factors for optimizing a FSM design is the choice of state coding, which influences the complexity of the logic functions, the hardware costs of the circuits, timing issues, power usage, etc. There are several options like binary encoding, gray encoding, one-hot encoding, etc. The choice of the designer depends on the factors like technology, design specifications, etc.<br /><span style="font-weight: bold;"><br />One-hot encoding</span> <br /><br />In one-hot encoding only one bit of the state vector is asserted for any given state. All other state bits are zero. Thus if there are <span style="font-style: italic;">n</span> states then <span style="font-style: italic;">n</span> state flip-flops are required. As only one bit remains logic high and rest are logic low, it is called as One-hot encoding.<br /><span style="font-style: italic;">Example</span>: If there is a FSM, which has 5 states. Then 5 flip-flops are required to implement the FSM using one-hot encoding. The states will have the following values:<br /><span style="font-style: italic;">S0 </span>- 10000<br /><span style="font-style: italic;">S1 </span>- 01000<br /><span style="font-style: italic;">S2 </span>- 00100<br /><span style="font-style: italic;">S3 </span>- 00010<br /><span style="font-style: italic;">S4</span> - 00001<br /><br /><span style="font-weight: bold;">Advantages</span><br /><ul><li>State decoding is simplified, since the state bits themselves can be used directly to check whether the FSM is in a particular state or not. Hence additional logic is not required for decoding, this is extremely advantageous when implementing a big FSM.</li><li>Low switching activity, hence resulting low power consumption, and less prone to glitches.</li><li>Modifying a design is easier. Adding or deleting a state and changing state transition equations (combinational logic present in FSM) can be done without affecting the rest of the design.</li><li>Faster than other encoding techniques. Speed is independent of number of states, and depends only on the number of transitions into a particular state.</li><li>Finding the critical path of the design is easier (static timing analysis).</li><li>One-hot encoding is particularly advantageous for FPGA implementations. If a big FSM design is implemented using FPGA, regular encoding like binary, gray, etc will use fewer flops for the state vector than one-hot encoding, but additional logic blocks will be required to encode and decode the state. But in FPGA each logic block contains one or more flip-flops (<a href="http://only-vlsi.blogspot.com/2008/05/field-programmable-gate-array.html">click here</a> to know why?) hence due to presence of encoding and decoding more logics block will be used by regular encoding FSM than one-hot encoding FSM.<br /></li></ul><span style="font-weight: bold;">Disadvantages</span><br /><ul><li>The only disadvantage of using one-hot encoding is that it required more flip-flops than the other techniques like binary, gray, etc. The number of flip-flops required grows linearly with number of states. <span style="font-style: italic;">Example</span>: If there is a FSM with 38 states. One-hot encoding requires 38 flip-flops where as other require 6 flip-flops only.</li></ul>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-85242532235208903572008-06-03T09:52:00.000-07:002008-06-03T09:56:07.235-07:00Microprocessor Interview Questions - 51. Why are program counter and stack pointer 16-bit registers?<br /><a href="javascript:showHide('div1')">Answer</a><br /><div id="div1" style="display:none;"><br />Program Counter (PC) and Stack Pointer (SP) are basically used to hold 16-bit memory addresses.PC stores the 16-bit memory address of the next instruction to be fetched. SP stores address of stack's starting block. <br /></div><br />2. What happens during DMA transfer?<br /><a href="javascript:showHide('div2')">Answer</a><br /><div id="div2" style="display:none;"><br />During DMA transfers DMA controller takes control of the data transfer, and the processor will carry out other tasks.<br /></div><br />3. Define ISR.<br /><a href="javascript:showHide('div3')">Answer</a><br /><div id="div3" style="display:none;"><br /> An interrupt handler, also known as an interrupt service routine (ISR), is a callback subroutine in an operating system or device driver whose execution is triggered by the reception of an interrupt. Whenever there is an interrupt the processor jumps to ISR and executes it.<br /></div><br />4. Define PSW.<br /><a href="javascript:showHide('div4')">Answer</a><br /><div id="div4" style="display:none;"><br />The Program Status Word (PSW) is a register which contains information about the current program status used by the operating system and the underlying hardware. The PSW includes the instruction address, condition code, and other fields. In general, the PSW is used to control instruction sequencing and to hold and indicate the status of the system in relation to the program currently being executed. The active or controlling PSW is called the current PSW. By storing the current PSW during an interruption, the status of the CPU can be preserved for subsequent inspection. By loading a new PSW or part of a PSW, the state of the CPU can be initialized or changed.<br /></div><br />5. What are the execution modes available in x86 processors?<br /><a href="javascript:showHide('div5')">Answer</a><br /><div id="div5" style="display:none;"><br /> * Real mode (16-bit)<br /> * Protected mode (16-bit and 32-bit)<br /> * Virtual 8086 mode (16-bit)<br /> * Unreal mode (32-bit)<br /> * System Management Mode (16-bit)<br /> * Long mode (64-bit)<br /></div><br />6. What is meant real mode?<br /><a href="javascript:showHide('div6')">Answer</a><br /><div id="div6" style="display:none;"><br /> Real mode is an execution/operating mode of 80286 and later x86-compatible CPUs. Real mode is characterized by a 20 bit segmented memory address space, where a maximum of 1 MB of memory can be addressed, direct software access to BIOS routines and peripheral hardware, and no concept of memory protection or multitasking at the hardware level. All x86 CPUs in the 80286 series and later start in real mode at power-on (earlier CPUs had only one operational mode, which is equivalent to real mode in later chips).<br /></div><br />7. What is protected mode?<br /><a href="javascript:showHide('div7')">Answer</a><br /><div id="div7" style="display:none;"><br /> Protected mode allows system software to utilize features such as virtual memory, paging, safe multi-tasking, and other features designed to increase an operating system's control over application software.<br /> When a processor that supports x86 protected mode is powered on, it begins executing instructions in real mode, in order to maintain backwards compatibility with earlier x86 processors. Protected mode may only be entered after the system software sets up several descriptor tables and enables the Protection Enable (PE) bit in the Control Register 0.<br /></div><br />8. What is virtual 8086 mode?<br /><a href="javascript:showHide('div8')">Answer</a><br /><div id="div8" style="display:none;"><br /> Virtual real mode or VM86, allows the execution of real mode applications that are incapable of running directly in protected mode. It uses a segmentation scheme identical to that of real mode, and also uses 21-bit addressing - resulting in linear addressing - so it is subject to paging.<br /></div><br />9. What is unreal mode?<br /><a href="javascript:showHide('div9')">Answer</a><br /><div id="div9" style="display:none;"><br /> Unreal mode, also known as big real mode, huge real mode, or flat real mode, is a variant of real mode. one or more data segment registers will be loaded with 32-bit addresses and limits.<br /></div><br />10. What is the difference between ISR and a function call?<br /><a href="javascript:showHide('div10')">Answer</a><br /><div id="div10" style="display:none;"><br /> ISR has no return value, where as a function call has the return value.<br /></div>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-21115703005615389732008-05-28T09:23:00.000-07:002008-06-21T07:24:41.437-07:00SoC : System-On-a-ChipSystem-on-a-chip (SoC) refers to integrating all components of an electronic system into a single integrated circuit (chip). A SoC can include the integration of:<br /><ul><li>Ready made sub-circuits (IP)</li><li>One or more microcontroller, microprocessor or DSP core(s)</li><li>Memory components</li><li>Sensors</li><li>Digital, Analog, or Mixed signal components</li><li>Timing sources, like oscillators and phase-locked loops</li><li>Voltage regulators and power management circuits<br /></li></ul>The blocks of SoC are connected by a special bus, such as the AMBA bus. DMA controllers are used for routing the data directly between external interfaces and memory, by-passing the processor core and thereby increasing the data throughput of the SoC. SoC is widely used in the area of embedded systems. SoCs can be fabricated by several technologies, like, Full custom, Standard cell, FPGA, etc. SoC designs are usually power and cost effective, and more reliable than the corresponding multi-chip systems. A programmable SoC is known as PSoC.<br /><br /><span style="font-weight: bold;">Advantages</span> of SoC are:<br /><ul><li>Small size, reduction in chip count</li><li>Low power consumption</li><li>Higher reliability</li><li>Lower memory requirements</li><li>Greater design freedom</li><li>Cost effective<br /></li></ul><span style="font-weight: bold;">Design Flow</span><br /><br />SoC consists of both hardware and software( to control SoC components). The aim of SoC design is to develop hardware and software in parallel. SoC design uses pre-qualified hardware, along with their software (drivers) which control them. The hardware blocks are put together using CAD tools; the software modules are integrated using a software development environment. The SoC design is then programmed onto a <a href="http://only-vlsi.blogspot.com/2008/05/field-programmable-gate-array.html">FPGA</a>, which helps in testing the behavior of SoC. Once SoC design passes the testing it is then sent to the place and route process. Then it will be fabricated. The chips will be completely tested and verified.Unknownnoreply@blogger.com1tag:blogger.com,1999:blog-2897681058883783104.post-41498076490238798872008-05-25T07:55:00.000-07:002008-05-25T07:58:52.036-07:00VLSI Interview Questions - 61. Why is NAND gate preferred over NOR gate for fabrication?<br /><a href="javascript:showHide('div1')">Answer</a><br /><div id="div1" style="display:none;"><br />NAND is a better gate for design than NOR because at the transistor level the mobility of electrons of NAND is normally three times that of holes compared to NOR and thus the NAND is a faster gate. The gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND (the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance PMOSs are in series connection which again increases the resistance).<br /></div><br />2. Which transistor has higher gain: BJT or MOSFET and why?<br /><a href="javascript:showHide('div2')">Answer</a><br /><div id="div2" style="display:none;"><br />BJT has higher gain because it has higher transconductance.This is because the current in BJT is exponentially dependent on input where as in MOSFET it is square law.<br /></div><br />3. Why PMOS and NMOS are sized equally in a transmission gates?<br /><a href="javascript:showHide('div3')">Answer</a><br /><div id="div3" style="display:none;"><br />In transmission gate, PMOS and NMOS aid each other rather than competing with each other. So they are sized similarly.<br /></div><br />4. What is SCR?<br /><a href="javascript:showHide('div4')">Answer</a><br /><div id="div4" style="display:none;"><br />A silicon-controlled rectifier (or semiconductor-controlled rectifier) is a 4-layer solid state device that controls current flow.<br /> An SCR is a type of rectifier, controlled by a logic gate signal. It is a 4-layered, 3-terminal device. A p-type layer acts as an anode and an n-type layer as a cathode; the p-type layer closer to the n-type(cathode) acts as a gate.<br /></div><br />5. In CMOS digital design, why is the size of PMOS is generally higher than that of the NMOS?<br /><a href="javascript:showHide('div5')">Answer</a><br /><div id="div5" style="display:none;"><br />In PMOS the carriers are holes whose mobility is less than the electrons, the carriers in NMOS. That means PMOS is slower than NMOS. In CMOS technology, NMOS helps in pulling down the output to ground and PMOS helps in pulling up the output to Vdd. If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output node. If we have a larger PMOS than there will be more carriers to charge the node quickly and overcome the slow nature of PMOS. All this is done to get equal rise and fall times for the output node. <br /></div><br />6. What is slack?<br /><a href="javascript:showHide('div6')">Answer</a><br /><div id="div6" style="display:none;"><br />The slack is the time delay difference from the expected delay to the actual delay in a particular path. Slack can be positive or negative.<br /></div><br />7. What is latch up?<br /><a href="javascript:showHide('div7')">Answer</a><br /><div id="div7" style="display:none;"><br />A latchup is the inadvertent creation of a low-impedance path between the power supply rails of an electronic component, triggering a parasitic structure(The parasitic structure is usually equivalent to a thyristor or SCR), which then acts as a short circuit, disrupting proper functioning of the part. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical over stress - EOS. <br /></div><br />8. Why is the size of inverters in buffer design gradually increased? Why not give the output of a circuit to one large inverter?<br /><a href="javascript:showHide('div8')">Answer</a><br /><div id="div8" style="display:none;"><br />Because circuit can not drive the high output load straight away, so the load is gradually increased, by gradually increasing the size of inverters to get an optimized performance. <br /></div><br />9. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus? <br /><a href="javascript:showHide('div9')">Answer</a><br /><div id="div9" style="display:none;"><br />The charge sharing problem occurs when the charge which is stored at the output node in the phase is shared among the output or junction capacitances of transistors which are in the evaluation phase. Charge sharing may degrade the output voltage level or even cause erroneous output value.<br /> In the serially connected NMOS logic the input capacitance of each gate shares the charge with the load capacitance by which the logical levels drastically mismatched than that of the desired once. To eliminate this load capacitance must be very high compared to the input capacitance of the gate, which is generally 10 times.<br /></div><br />10. What happens to delay if load capacitance is increased? <br /><a href="javascript:showHide('div10')">Answer</a><br /><div id="div10" style="display:none;"><br />Delay increases.<br /></div>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-74006501987747008702008-05-20T07:21:00.000-07:002008-11-12T22:39:58.251-08:00Complex Programmable Logic DeviceA complex programmable logic device (CPLD) is a semiconductor device containing programmable blocks called macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations. CPLD has complexity between that of PALs and <a href="http://only-vlsi.blogspot.com/2008/05/field-programmable-gate-array.html">FPGA</a>s. It can has up to about 10,000 gates. CPLDs offer very predictable timing characteristics and are therefore ideal for critical control applications.<br /><br /><span style="font-weight: bold;">Applications</span><br /><ul><li>CPLDs are ideal for critical, high-performance control applications.</li><li>CPLD can be used for digital designs which perform boot loader functions.</li><li>CPLD is used to load configuration data for an FPGA from non-volatile memory.</li><li>CPLD are generally used for small designs, for example, they are used in simple applications such as address decoding.</li><li>CPLDs are often used in cost-sensitive, battery-operated portable applications, because of its small size and low-power usage.<br /></li></ul><span style="font-weight: bold;">Architecture</span><br /><br />A CPLD contains a bunch of programmable functional blocks (FB) whose inputs and outputs are connected together by a global interconnection matrix. The global interconnection matrix is reconfigurable, so that we can change the connections between the FBs. There will be some I/O blocks which allow us to connect CPLD to external world. The block diagram of architecture of CPLD is shown below.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhM5y09nUs36RXvLV9pjcVu401XXGktPUZ_aFKIGWiLip6Lz5PwSR7Ktg26MONRcxVVzIx1DjYBDoRu6A-MCmGKHiGURC6HEaeqmmBDGy-wZ1eOKF1_YAd5Bg9YF3fFXW-506c_kTn6SpC_/s1600-h/cpld1_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhM5y09nUs36RXvLV9pjcVu401XXGktPUZ_aFKIGWiLip6Lz5PwSR7Ktg26MONRcxVVzIx1DjYBDoRu6A-MCmGKHiGURC6HEaeqmmBDGy-wZ1eOKF1_YAd5Bg9YF3fFXW-506c_kTn6SpC_/s400/cpld1_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5202465510837683410" border="0" /></a><br />The programmable functional block typically looks like the one shown below. There will be an array of AND gates which can be programed. The OR gates are fixed. But each manufacturer has their way of building the functional block. A registered output can be obtained by manipulating the feedback signals obtained from the OR ouputs.<br /><span style="font-weight: bold;"><br /></span><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi9OqIMO5IbVqgXIca3KCgMKkSUKv_BDP4vGwEnVv5P4nuBJYxdx9v_dmRHlbgL7s9aWxwkTeytmwAYp87KtnaJVvX6oRwlXKJdqpsvwtp0He5Av6pJO5qgKnM1x6ax5_c4zalzbjmkcqj9/s1600-h/cpld2_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi9OqIMO5IbVqgXIca3KCgMKkSUKv_BDP4vGwEnVv5P4nuBJYxdx9v_dmRHlbgL7s9aWxwkTeytmwAYp87KtnaJVvX6oRwlXKJdqpsvwtp0He5Av6pJO5qgKnM1x6ax5_c4zalzbjmkcqj9/s400/cpld2_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5202465575262192866" border="0" /></a><span style="font-weight: bold;"><br />CPLD Programming</span><br /><br />The design is first coded in HDL (Verilog or VHDL), once the code is validated (simulated and synthesized). During synthesis the target device(CPLD model) is selected, and a technology-mapped net list is generated. The net list can then be fitted to the actual CPLD architecture using a process called place-and-route, usually performed by the CPLD company's proprietary place-and-route software. Then the user will do some verification processes. If every thing is fine, he will use the CPLD, else he will reconfigure it.Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-82315470094518733452008-05-19T04:08:00.000-07:002009-05-31T07:11:25.816-07:00Introduction to Digital Logic Design>> <a style="font-weight: bold;" href="http://only-vlsi.blogspot.com/2008/05/introduction-to-digital-logic.html#intro">Introduction</a><br />>> <a style="font-weight: bold;" href="http://only-vlsi.blogspot.com/2008/05/introduction-to-digital-logic.html#bns">Binary Number System</a><br />>> <a style="font-weight: bold;" href="http://only-vlsi.blogspot.com/2008/05/introduction-to-digital-logic.html#comp">Complements</a><br />>> <a style="font-weight: bold;" href="http://only-vlsi.blogspot.com/2008/05/introduction-to-digital-logic.html#2vs1">2's Complement vs 1's Complement</a><br />>> <a style="font-weight: bold;" href="http://only-vlsi.blogspot.com/2008/05/introduction-to-digital-logic.html#bl">Binary Logic</a><br />>> <a style="font-weight: bold;" href="http://only-vlsi.blogspot.com/2008/05/introduction-to-digital-logic.html#lg">Logic Gates</a><br /><br /><br /><a style="font-weight: bold;" name="intro">Introduction</a><br /><br />The fundamental idea of digital systems is to represent data in discrete form (Binary: ones and zeros) and processing that information. Digital systems have led to many scientific and technological advancements. Calculators, computers, are the examples of digital systems, which are widely used for commercial and business data processing. The most important property of a digital system is its ability to follow a sequence of steps to perform a task called program, which does the required data processing. The following diagram shows how a typical digital system will look like.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhhmEs-GQwqhnFhQxh50Qok4Yx3wAerAzDe2TJFDycjoT9gnaV0Gevlj4RFAqAHR4uyDTZCYXBSWhLKIQMLQNiRYRs_ltOfTjMJO9MoCPi9Q85uw4lxrqD-Xl_fgtL0-aVMALFUm7XJZeX/s1600-h/dld1_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhhmEs-GQwqhnFhQxh50Qok4Yx3wAerAzDe2TJFDycjoT9gnaV0Gevlj4RFAqAHR4uyDTZCYXBSWhLKIQMLQNiRYRs_ltOfTjMJO9MoCPi9Q85uw4lxrqD-Xl_fgtL0-aVMALFUm7XJZeX/s400/dld1_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5202045587590186130" border="0" /></a><br />Representing the data in ones and zeros, i.e. in binary system is the root of the digital systems. All the digital system store data in binary format. Hence it is very important to know about binary number system. Which is explained below.<br /><br /><a style="font-weight: bold;" name="bns">Binary Number System</a><br /><br />The binary number system, or base-2 number system, is a number system that represents numeric values using two symbols, usually 0 and 1. The base-2 system is a positional notation with a radix of 2. Owing to its straightforward implementation in digital electronic circuitry using logic gates, the binary system is used internally by all computers. Suppose we need to represent 14 in binary number system.<br />14 - 01110 - 0x2<sup>4</sup> + 1x2<sup>3</sup> + 1x2<sup>2</sup> + 1x2<sup>1</sup> + 0x2<sup>0</sup><br />similarly,<br />23 - 10111 - 1x2<sup>4</sup> + 0x2<sup>3</sup> + 1x2<sup>2</sup> + 1x2<sup>1</sup> + 1x2<sup>0</sup><br /><br /><a style="font-weight: bold;" name="comp">Complements</a><br /><br />In digital systems, complements are used to simplify the subtraction operation. There are two types of complements they are:<br /><span style="font-style: italic;">The r's Complement</span><br /><span style="font-style: italic;">The (r-1)'s Complement</span><br /><br />Given:<br /><ul><li>N a positive number.</li><li>r base of the number system.</li><li>n number of digits.</li><li>m number of digits in fraction part.<br /></li></ul>The r's complement of N is defined as r<sup>n</sup> - N for N not equal to 0 and 0 for N=0.<br /><br />The (r-1)'s Complement of N is defined as r<sup>n</sup> - r<sup>m</sup> - N.<br /><br /><span style="font-style: italic;">Subtraction with r's complement:</span><br /><br />The subtraction of two positive numbers (M-N), both are of base r. It is done as follows:<br />1. Add M to the r's complement of N.<br />2. Check for an end carry:<br />(a) If an end carry occurs, ignore it.<br />(b) If there is no end carry, the negative of the r's complement of the result obtained in step-1 is the required value.<br /><br /><span style="font-style: italic;">Subtraction with (r-1)'s complement:</span><br /><br />The subtraction of two positive numbers (M-N), both are of base r. It is done as follows:<br />1. Add M to the (r-1)'s complement of N.<br />2. Check for an end carry:<br />(a) If an end carry occurs, add 1 to the result obtained in step-1.<br />(b) If there is no end carry, the negative of the (r-1)'s complement of the result obtained in step-1 is the required value.<br /><br />For a binary number system the complements are: 2's complement and 1's complement.<br /><br /><a style="font-weight: bold;" name="2vs1">2's Complement vs 1's Complement</a><br /><br />The only advantage of 1's complement is that it can be calculated easily, just by changing 0s into 1s and 1s into 0s. The 2's complement is calculated in two ways, (i) add 1 to the 1's complement of the number, and (ii) leave all the leading 0s in the least significant positions and keep first 1 unchanged, and then change 0s into 1s and 1s into 0s.<br /><br />The advantages of 2's complement over 1's complement are:<br />(i) For subtraction with complements, 2's complement requires only one addition operation, where as for 1's complement requires two addition operations if there is an end carry.<br />(ii) 1's complement has two arithmetic zeros, all 0s and all 1s.<br /><br /><a style="font-weight: bold;" name="bl">Binary Logic</a><br /><br />Binary logic contains only two discrete values like, 0 or 1, true or false, yes or no, etc. Binary logic is similar to Boolean algebra. It is also called as boolean logic. In boolean algebra there are three basic operations: AND, OR, and NOT.<br /><span style="font-style: italic; font-weight: bold;">AND</span>: Given two inputs x, y the expression x.y or simply xy represents "x AND y" and equals to 1 if both x and y are 1, otherwise 0.<br /><span style="font-style: italic; font-weight: bold;">OR</span>: Given two inputs x, y the expression x+y represents "x OR y" and equals to 1 if at least one of x and y is 1, otherwise 0.<br /><span style="font-style: italic; font-weight: bold;">NOT</span>: Given x, the expression x' represents NOT(x) equals to 1 if x is 0, otherwise 0. NOT(x) is x complement.<br /><br /><a style="font-weight: bold;" name="lg">Logic Gates</a><br /><br />A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. Because the output is also a logic-level value, an output of one logic gate can connect to the input of one or more other logic gates. The logic gate use binary logic or boolean logic. AND, OR, and NOT are the three basic logic gates of digital systems. Their symbols are shown below.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhoXDoIo2UyzIAqdgL0TrbzvCzdQbZzFbNCmeyrm2G9-GybyFU79LPfkv5piC34Mi43xoEcVyF3LBBz0_WHRsj0qKAlDf0s3XbIP-XPyOiiBsZLn4b1u8ZMjbh-xg-rqfDaJgBFOIWKTIrQ/s1600-h/dld2_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhoXDoIo2UyzIAqdgL0TrbzvCzdQbZzFbNCmeyrm2G9-GybyFU79LPfkv5piC34Mi43xoEcVyF3LBBz0_WHRsj0qKAlDf0s3XbIP-XPyOiiBsZLn4b1u8ZMjbh-xg-rqfDaJgBFOIWKTIrQ/s400/dld2_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5202045652014695586" border="0" /></a><br />AND and OR gates can have more than two inputs. The above diagram shows 2 input AND and OR gates. The truth tables of AND, OR, and NOT logic gates are as follows.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi5SUThGAQ4_DsZjmN6rCmxPtGyIwm5Myc9IFv4x03ILuD3h3WxYibOF16AJZ7EIFtwj3GI3oQSVsMhSp7N-Ri11AvyD64SeqLp6KTxsYBZbqU_mV-GWzlqMwea04_J9p780R02arSPdemT/s1600-h/tt1_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi5SUThGAQ4_DsZjmN6rCmxPtGyIwm5Myc9IFv4x03ILuD3h3WxYibOF16AJZ7EIFtwj3GI3oQSVsMhSp7N-Ri11AvyD64SeqLp6KTxsYBZbqU_mV-GWzlqMwea04_J9p780R02arSPdemT/s400/tt1_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5202045518870709378" border="0" /></a>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-46056969152267493782008-05-18T05:05:00.000-07:002008-05-26T07:42:32.158-07:00Microprocessor Interview Questions - 41. What is the size of flag register of 8086 processor?<br /><a href="javascript:showHide('div1')">Answer</a><br /><div id="div1" style="display: none;"><br /> 16-bit.<br /></div><br />2. How many pin IC 8086 is?<br /><a href="javascript:showHide('div2')">Answer</a><br /><div id="div2" style="display: none;"><br /> 40 pin dual in-line package.<br /></div><br />3. What is the Maximum clock frequency of 8086?<br /><a href="javascript:showHide('div3')">Answer</a><br /><div id="div3" style="display: none;"><br /> 5 Mhz is the Maximum clock frequency of 8086.<br /></div><br />4. What is meant by instruction cycle?<br /><a href="javascript:showHide('div4')">Answer</a><br /><div id="div4" style="display: none;"><br /> An instruction cycle also known as fetch-and-execute cycle and fetch-decode-execute cycle, is the time period during which a computer reads and processes a machine language instruction from its memory.<br /></div><br />5. What is Von Neumann architecture?<br /><a href="javascript:showHide('div5')">Answer</a><br /><div id="div5" style="display: none;"><br /> The Von Neumann architecture is a computer design model that uses a processing unit and a single separate storage structure to hold both instructions and data. The instruction/data is read from storage and executed by the processing unit. It is also known as "stored-program computer".<br /></div><br />6. What is the main difference between 8086 and 8085?<br /><a href="javascript:showHide('div6')">Answer</a><br /><div id="div6" style="display: none;"><br /> 8086 is 16-bit microprocessor, where as 8085 is a 8-bit microprocessor.<br /></div><br />7. What does EAX mean?<br /><a href="javascript:showHide('div7')">Answer</a><br /><div id="div7" style="display: none;"><br /> With the advent of the 32-bit 80386 processor, the 16-bit general-purpose registers, base registers, index registers, instruction pointer, and FLAGS register, but not the segment registers, were expanded to 32 bits. This is represented by prefixing an "E" (for Extended) to the register opcodes, thus the expanded AX became EAX.(Similarly BX became EBX, SI became ESI and so on).<br /></div><br />8. What type of instructions are available in instruction set of 8086?<br /><a href="javascript:showHide('div8')">Answer</a><br /><div id="div8" style="display: none;"><br /><ul><li>Data Instructions</li><li>Arithmetic Instructions</li><li>Logic Instructions</li><li>Control Instructions</li><li>Other - setting/clearing flag bits, stack operations, software interrupts, etc.</li></ul><br /></div><br />9. How is Stack Pointer affected when a PUSH and POP operations are performed?<br /><a href="javascript:showHide('div9')">Answer</a><br /><div id="div9" style="display: none;"><br /> When PUSH operation is performed the SP value is decreased by 2. When POP operation is performed the SP value is increased by 2.<br /></div><br />10. What are SIM and RIM instructions?<br /><a href="javascript:showHide('div10')">Answer</a><br /><div id="div10" style="display: none;"><br /> SIM - Set Interrupt Mask, is used to mask the hardware interrupts. RIM - Read Interrupt Mask, is used to check whether the interrupt is Masked or not.<br /></div>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-31427841757113706372008-05-17T06:40:00.000-07:002008-05-17T06:46:37.177-07:00Microprocessor Interview Questions - 31. How many bits processor is 8086? <br /><a href="javascript:showHide('div1')">Answer</a><br /><div id="div1" style="display:none;"><br /> 16-bit processor.<br /></div><br />2. What are the sizes of data bus and address bus in 8086?<br /><a href="javascript:showHide('div2')">Answer</a><br /><div id="div2" style="display:none;"><br /> 16-bit data bus, and 20-bit address bus.<br /></div><br />3. What is the maximum addressable memory of 8086?<br /><a href="javascript:showHide('div3')">Answer</a><br /><div id="div3" style="display:none;"><br /> 1MByte, because 20-bit address bus.<br /></div><br />4. How are 32-bit addresses stored in 8086?<br /><a href="javascript:showHide('div4')">Answer</a><br /><div id="div4" style="display:none;"><br />32-bit addresses are stored in "SEGMENT:OFFSET" format. SEGMENT and OFFSET are 16-bit values.<br /><b>ADDRESS = (SEGMENT* 16) + OFFSET</b><br /></div><br />5. What are the 16-bit registers that are available in 8086?<br /><a href="javascript:showHide('div5')">Answer</a><br /><div id="div5" style="display:none;"><br />The following are the 16-bit registers that are available in 8086. <br /><br /><span style="font-weight:bold;">8 general purpose registers:</span><br />AX - Accumulator Register<br />Bx - Base Register<br />CX - Count Register<br />DX - Data Register<br />SP - Stack Pointer<br />BP - Base Pointer<br />SI - Source Index<br />DI - Destination Index<br /><br /><span style="font-weight:bold;">4 segment registers:</span><br />CS - Code Segment<br />DS - Data Segment<br />SS - Stack Segment<br />ES - Extra Segment<br /><br /><span style="font-weight:bold;">Others:</span><br />IP - Instruction Pointer<br />Flag register<br /><br /></div><br />6. What are the different types of address modes available in 8086?<br /><a href="javascript:showHide('div6')">Answer</a><br /><div id="div6" style="display:none;"><br /><b>Implied</b> - the data value/data address is implicitly associated with the instruction.<br /><b>Register</b> - references the data in a register or in a register pair.<br /><b>Immediate</b> - the data is provided in the instruction.<br />Direct - the instruction operand specifies the memory address where data is located.<br /><b>Register indirect</b> - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers.<br /><b>Based</b> - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides.<br /><b>Indexed</b> - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides.<br /><b>Based Indexed</b> - the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides.<br /><b>Based Indexed with Offset</b> - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides.<br /></div><br />7. How many flags are available in flag register? What are they?<br /><a href="javascript:showHide('div7')">Answer</a><br /><div id="div7" style="display:none;"><br />9 flags are available, they are: <br /> Overflow Flag<br /> Direction Flag<br /> Interrupt-enable Flag<br /> Trace/Trap Flag<br /> Sign Flag<br /> Zero Flag<br /> Auxiliary carry Flag<br /> Parity Flag<br /> Carry Flag <br /></div><br />8. Explain the functioning of IP (instruction pointer).<br /><a href="javascript:showHide('div8')">Answer</a><br /><div id="div8" style="display:none;"><br />IP always points to next instruction to be executed. Offset address is relative to CS (which points at the segment containing the current program). The next instruction address is obtained using IP.<br /></div><br />9. What are the various types of interrupts present in 8086?<br /><a href="javascript:showHide('div9')">Answer</a><br /><div id="div9" style="display:none;"><br /> INTR - maskable hardware interrupt<br /> NMI - non-maskable interrupt<br /> Software interrupts<br /></div><br />10. How many segments are present in 8086? What are they?<br /><a href="javascript:showHide('div10')">Answer</a><br /><div id="div10" style="display:none;"><br /> 4 segments are available in 8086. They are:<br /> Code segment<br /> Data segment<br /> Extra segment<br /> Stack segment<br /></div>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-61917917423212771842008-05-15T05:36:00.000-07:002008-11-12T22:40:19.825-08:00Digital Design Interview Questions - 51. Expand the following: PLA, PAL, CPLD, FPGA.<br /><a href="javascript:showHide('div1')">Answer</a><br /><div id="div1" style="display: none;"><br />PLA - Programmable Logic Array<br />PAL - Programmable Array Logic<br />CPLD - Complex Programmable Logic Device<br />FPGA - Field-Programmable Gate Array<br /></div><br />2. Implement the functions: X = A'BC + ABC + A'B'C' and Y = ABC + AB'C using a PLA.<br /><a href="javascript:showHide('div2')">Answer</a><br /><div id="div2" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi_RAOgu4OL3n891oWaXb8_TgeyCm_xoNYU5JD8_5leEU1pO13r0vcy6dmrzY-E0E6p5kcRJy6vX_Aj-i0CJn_lsbNroaxq6m4TjYzjtDqVic4qT3rRQNiOzHQ2W52CeoG6-HpU39bFR3UQ/s1600-h/pla_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi_RAOgu4OL3n891oWaXb8_TgeyCm_xoNYU5JD8_5leEU1pO13r0vcy6dmrzY-E0E6p5kcRJy6vX_Aj-i0CJn_lsbNroaxq6m4TjYzjtDqVic4qT3rRQNiOzHQ2W52CeoG6-HpU39bFR3UQ/s400/pla_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5199855656780399714" border="0" /></a><br /></div><br />3. What are PLA and PAL? Give the differences between them.<br /><a href="javascript:showHide('div3')">Answer</a><br /><div id="div3" style="display: none;"><br /> Programmable Logic Array is a programmable device used to implement combinational logic circuits. The PLA has a set of programmable AND planes, which link to a set of programmable OR planes, which can then be conditionally complemented to produce an output.<br /> PAL is programmable array logic, like PLA, it also has a wide, programmable AND plane. Unlike a PLA, the OR plane is fixed, limiting the number of terms that can be ORed together.<br /> Due to fixed OR plane PAL allows extra space, which is used for other basic logic devices, such as multiplexers, exclusive-ORs, and latches. Most importantly, clocked elements, typically flip-flops, could be included in PALs. PALs are also extremely fast.<br /></div><br />4. What is LUT?<br /><a href="javascript:showHide('div4')">Answer</a><br /><div id="div4" style="display: none;"><br />LUT - Look-Up Table. An n-bit look-up table can be implemented with a multiplexer whose select lines are the inputs of the LUT and whose inputs are constants. An n-bit LUT can encode any n-input Boolean function by modeling such functions as truth tables. This is an efficient way of encoding Boolean logic functions, and LUTs with 4-6 bits of input are in fact the key component of modern FPGAs.<br /></div><br />5. What is the significance of FPGAs in modern day electronics? (Applications of FPGA.)<br /><a href="javascript:showHide('div5')">Answer</a><br /><div id="div5" style="display: none;"><br /><ul><li>ASIC prototyping: Due to high cost of ASIC chips, the logic of the application is first verified by dumping HDL code in a FPGA. This helps for faster and cheaper testing. Once the logic is verified then they are made into ASICs.</li><li>Very useful in applications that can make use of the massive parallelism offered by their architecture. Example: code breaking, in particular brute-force attack, of cryptographic algorithms.</li><li>FPGAs are sued for computational kernels such as FFT or Convolution instead of a microprocessor.</li><li>Applications include digital signal processing, software-defined radio, aerospace and defense systems, medical imaging, computer vision, speech recognition, cryptography, bio-informatics, computer hardware emulation and a growing range of other areas.</li></ul><br /></div><br />6. What are the differences between CPLD and FPGA.<br /><a href="javascript:showHide('div6')">Answer</a><br /><div id="div6" style="display: none;"><br /><br /></div><br />7. Compare and contrast FPGA and ASIC digital designing.<br /><a href="javascript:showHide('div7')">Answer</a><br /><div id="div7" style="display: none;"><br /><a href="http://only-vlsi.blogspot.com/2008/05/fpga-vs-asic.html">Click here.</a><br /></div><br />8. Give True or False.<br />(a) CPLD consumes less power per gate when compared to FPGA.<br />(b) CPLD has more complexity than FPGA<br />(c) FPGA design is slower than corresponding ASIC design.<br />(d) FPGA can be used to verify the design before making a ASIC.<br />(e) PALs have programmable OR plane.<br />(f) FPGA designs are cheaper than corresponding ASIC, irrespective of design complexity.<br /><a href="javascript:showHide('div8')">Answer</a><br /><div id="div8" style="display: none;"><br />(a) False<br />(b) False<br />(c) True<br />(d) True<br />(e) False<br />(f) False<br /></div><br />9. Arrange the following in the increasing order of their complexity: FPGA,PLA,CPLD,PAL.<br /><a href="javascript:showHide('div9')">Answer</a><br /><div id="div9" style="display: none;"><br />Increasing order of complexity: PLA, PAL, CPLD, FPGA.<br /></div><br />10. Give the FPGA digital design cycle.<br /><a href="javascript:showHide('div10')">Answer</a><br /><div id="div10" style="display: none;"><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglbokNbZrSvfNYxCUZCIL1p9fR4R_j8qIPYUYsuqx6CPABmEzT160xk-4ygPooZ_b8dcQEt6wvFNq1Tu_0tDO9TcgP-PCkTYlleJ3f7egpSds1GMvZRNGmrKLGfIZxgyASxoQcCrt2w2Mt/s1600-h/fpga_flow_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglbokNbZrSvfNYxCUZCIL1p9fR4R_j8qIPYUYsuqx6CPABmEzT160xk-4ygPooZ_b8dcQEt6wvFNq1Tu_0tDO9TcgP-PCkTYlleJ3f7egpSds1GMvZRNGmrKLGfIZxgyASxoQcCrt2w2Mt/s400/fpga_flow_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5200583542067922034" border="0" /></a><br /></div>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-71934532315457690512008-05-13T06:31:00.000-07:002008-11-12T22:40:19.842-08:00Programmable Logic ArrayIn Digital design, we often use a device to perform multiple applications. The device configuration is changed (reconfigured) by programming it. Such devices are known as programmable devices. It is used to build reconfigurable digital circuits. The following are the popular programmable device<br /><ul><li>PLA - Programmable Logic Array</li><li>PAL - Programmable Array Logic<br /></li><li>CPLD - Complex Programmable Logic Device (<a href="http://only-vlsi.blogspot.com/2008/05/complex-programmable-logic-device.html">Click here</a> <span style="text-decoration: underline;"></span>for more details)</li><li>FPGA - Field-Programmable Gate Array (<span style="text-decoration: underline;"></span><a href="http://only-vlsi.blogspot.com/2008/05/field-programmable-gate-array.html">Click here</a> for more details)<br /></li></ul><br /><span style="font-weight: bold;">PLA: Programmable Logic Array</span> is a programmable device used to implement combinational logic circuits. The PLA has a set of programmable AND planes, which link to a set of programmable OR planes, which can then be conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized in the sum of products canonical forms.<br /><br />Suppose we need to implement the functions: <span style="font-style: italic;">X = A'BC + ABC + A'B'C'</span> and <span style="font-style: italic;">Y = ABC + AB'C</span>. The following figures shows how PLA is configured. The big dots in the diagram are connections. For the first AND gate (left most), <span style="font-style: italic;">A</span> complement, <span style="font-style: italic;">B</span>, and <span style="font-style: italic;">C </span>are connected, which is first minterm of function <span style="font-style: italic;">X</span>. For second AND gate (from left), <span style="font-style: italic;">A</span>, <span style="font-style: italic;">B</span>, and <span style="font-style: italic;">C</span> are connected, which forms <span style="font-style: italic;">ABC</span>. Similarly for <span style="font-style: italic;">A'B'C'</span>, and <span style="font-style: italic;">AB'C</span>. Once the minterms are implemented. Now we have to combine them using OR gates to the functions <span style="font-style: italic;">X</span>, and <span style="font-style: italic;">Y</span>.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi_RAOgu4OL3n891oWaXb8_TgeyCm_xoNYU5JD8_5leEU1pO13r0vcy6dmrzY-E0E6p5kcRJy6vX_Aj-i0CJn_lsbNroaxq6m4TjYzjtDqVic4qT3rRQNiOzHQ2W52CeoG6-HpU39bFR3UQ/s1600-h/pla_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi_RAOgu4OL3n891oWaXb8_TgeyCm_xoNYU5JD8_5leEU1pO13r0vcy6dmrzY-E0E6p5kcRJy6vX_Aj-i0CJn_lsbNroaxq6m4TjYzjtDqVic4qT3rRQNiOzHQ2W52CeoG6-HpU39bFR3UQ/s400/pla_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5199855656780399714" border="0" /></a><br /> One application of a PLA is to implement the control over a data path. It defines various states in an instruction set, and produces the next state (by conditional branching).<br /><br />Note that the use of the word "Programmable" does not indicate that all PLAs are field-programmable; in fact many are mask-programmed during manufacture in the same manner as a ROM. This is particularly true of PLAs that are embedded in more complex and numerous integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are called FPLA (Field-programmable logic array).Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-2897681058883783104.post-13234469775452654962008-05-07T07:22:00.000-07:002008-11-12T22:40:19.955-08:00FPGA vs ASIC<span style="font-weight: bold;">Definitions</span><br /><br /><span style="font-weight: bold;">FPGA</span>: A Field-Programmable Gate Array (FPGA) is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. <span style="font-style: italic;">For complete details </span><a style="font-style: italic;" href="http://only-vlsi.blogspot.com/2008/05/field-programmable-gate-array.html">click here</a><span style="font-style: italic;">.</span><br /><br /><span style="font-weight: bold;">ASIC</span>: An application-specific integrated circuit (ASIC) is an integrated circuit designed for a particular use, rather than intended for general-purpose use. Processors, RAM, ROM, etc are examples of ASICs.<br /><br /><span style="font-weight: bold;">FPGA vs ASIC</span><br /><br /><span style="font-weight: bold;">Speed</span><br />ASIC rules out FPGA in terms of speed. As ASIC are designed for a specific application they can be optimized to maximum, hence we can have high speed in ASIC designs. ASIC can have hight speed clocks.<br /><br /><span style="font-weight: bold;">Cost</span><br />FPGAs are cost effective for small applications. But when it comes to complex and large volume designs (like 32-bit processors) ASIC products are cheaper.<br /><br /><span style="font-weight: bold;">Size/Area</span><br />FPGA are contains lots of LUTs, and routing channels which are connected via bit streams(program). As they are made for general purpose and because of re-usability. They are in-general larger designs than corresponding ASIC design. For example, LUT gives you both registered and non-register output, but if we require only non-registered output, then its a waste of having a extra circuitry. In this way ASIC will be smaller in size.<br /><br /><span style="font-weight: bold;">Power</span><br />FPGA designs consume more power than ASIC designs. As explained above the unwanted circuitry results wastage of power. FPGA wont allow us to have better power optimization. When it comes to ASIC designs we can optimize them to the fullest.<br /><br /><span style="font-weight: bold;">Time to Market</span><br />FPGA designs will till less time, as the design cycle is small when compared to that of ASIC designs. No need of layouts, masks or other back-end processes. Its very simple: Specifications -- HDL + simulations -- Synthesis -- Place and Route (along with static-analysis) -- Dump code onto FPGA and Verify. When it comes to ASIC we have to do floor planning and also advanced verification. The FPGA design flow eliminates the complex and time-consuming floor planning, place and route, timing analysis, and mask / re-spin stages of the project since the design logic is already synthesized to be placed onto an already verified, characterized FPGA device.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjxZ9ajEx0uCx27Pji5Y9qqooGBHIN1Sox9Yz79q_0jGmN-54X9Jg1eYyPMSa9LB3VejfwpjF0E55TLWwuxBkr5bytiRNb8lqN-pbIuwSftReu_kT2SSvUaNKxgooYZua_-bHtHnhBz7UOO/s1600-h/fpga_asic_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjxZ9ajEx0uCx27Pji5Y9qqooGBHIN1Sox9Yz79q_0jGmN-54X9Jg1eYyPMSa9LB3VejfwpjF0E55TLWwuxBkr5bytiRNb8lqN-pbIuwSftReu_kT2SSvUaNKxgooYZua_-bHtHnhBz7UOO/s400/fpga_asic_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5197641959686254530" border="0" /></a><br /><span style="font-weight: bold;">Type of Design</span><br />ASIC can have mixed-signal designs, or only analog designs. But it is not possible to design them using FPGA chips.<br /><br /><span style="font-weight: bold;">Customization</span><br />ASIC has the upper hand when comes to the customization. The device can be fully customized as ASICs will be designed according to a given specification. Just imagine implementing a 32-bit processor on a FPGA!<br /><br /><span style="font-weight: bold;">Prototyping</span><br />Because of re-usability of FPGAs, they are used as ASIC prototypes. ASIC design HDL code is first dumped onto a FPGA and tested for accurate results. Once the design is error free then it is taken for further steps. Its clear that FPGA may be needed for designing an ASIC.<br /><br /><span style="font-weight: bold;">Non Recurring Engineering/Expenses</span><br />NRE refers to the one-time cost of researching, designing, and testing a new product, which is generally associated with ASICs. No such thing is associated with FPGA. Hence FPGA designs are cost effective.<br /><br /><span style="font-weight: bold;">Simpler Design Cycle </span><br />Due to software that handles much of the routing, placement, and timing, FPGA designs have smaller designed cycle than ASICs.<br /><br /><span style="font-weight: bold;">More Predictable Project Cycle</span><br />Due to elimination of potential re-spins, wafer capacities, etc. FPGA designs have better project cycle.<br /><br /><span style="font-weight: bold;">Tools</span><br />Tools which are used for FPGA designs are relatively cheaper than ASIC designs.<br /><br /><span style="font-weight: bold;">Re-Usability</span><br />A single FPGA can be used for various applications, by simply reprogramming it (dumping new HDL code). By definition ASIC are application specific cannot be reused.Unknownnoreply@blogger.com2tag:blogger.com,1999:blog-2897681058883783104.post-22685994238279392272008-05-01T06:18:00.000-07:002008-11-12T22:40:20.314-08:00Field-Programmable Gate ArrayA <span style="font-style: italic;">Field-Programmable Gate Array</span> (FPGA) is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.<br /><br /><span style="font-weight: bold;">Applications</span><br /><ul><li>ASIC prototyping: Due to high cost of ASIC chips, the logic of the application is first verified by dumping HDL code in a FPGA. This helps for faster and cheaper testing. Once the logic is verified then they are made into ASICs.</li><li>Very useful in applications that can make use of the massive parallelism offered by their architecture. Example: code breaking, in particular brute-force attack, of cryptographic algorithms.</li><li>FPGAs are sued for computational kernels such as FFT or Convolution instead of a microprocessor.</li><li>Applications include digital signal processing, software-defined radio, aerospace and defense systems, medical imaging, computer vision, speech recognition, cryptography, bio-informatics, computer hardware emulation and a growing range of other areas.<br /></li></ul><span style="font-weight: bold;">Architecture</span><br /><br />FPGA consists of large number of "configurable logic blocks" (CLBs) and routing channels. Multiple I/O pads may fit into the height of one row or the width of one column in the array. In general all the routing channels have the same width. The block diagram of FPGA architecture is shown below.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiXAKFd8C-n39ihzG4VysFwK4gZ5hfBK-zJvaRJFvnIr5OiZWfoi4n1y0DnmC7LWDslduivd53i5SbcTKkrE-YHnH_FsNUZjFywagYwR1vZJ8gTeZTkJebyPsI0Lt4N4_CUzYMk_sWsxDuD/s1600-h/fpga_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiXAKFd8C-n39ihzG4VysFwK4gZ5hfBK-zJvaRJFvnIr5OiZWfoi4n1y0DnmC7LWDslduivd53i5SbcTKkrE-YHnH_FsNUZjFywagYwR1vZJ8gTeZTkJebyPsI0Lt4N4_CUzYMk_sWsxDuD/s400/fpga_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5202426740167902402" border="0" /></a><br /><span style="font-weight: bold;">CLB</span>: The CLB consists of an n-bit look-up table (LUT), a flip-flop and a 2x1 mux. The value n is manufacturer specific. Increase in n value can increase the performance of a FPGA. Typically n is 4. An n-bit lookup table can be implemented with a multiplexer whose select lines are the inputs of the LUT and whose inputs are constants. An n-bit LUT can encode any n-input Boolean function by modeling such functions as truth tables. This is an efficient way of encoding Boolean logic functions, and LUTs with 4-6 bits of input are in fact the key component of modern FPGAs. The block diagram of a CLB is shown below.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEihzd0nwIPQ6_h3Rj_LbtMDS_m-BKAMw1GdMJujjJPQsAfSHq4AtzhpvI1jEVDhnmAL5gQEn_f-v0Wy-2u2Vsf4iY0TfI0DWZBM8WLiE4f-_EWaBttGNtO6LmqlmMcFpjFB5FKB5IUBbKqA/s1600-h/fpga1_f.JPG"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEihzd0nwIPQ6_h3Rj_LbtMDS_m-BKAMw1GdMJujjJPQsAfSHq4AtzhpvI1jEVDhnmAL5gQEn_f-v0Wy-2u2Vsf4iY0TfI0DWZBM8WLiE4f-_EWaBttGNtO6LmqlmMcFpjFB5FKB5IUBbKqA/s400/fpga1_f.JPG" alt="" id="BLOGGER_PHOTO_ID_5195399362831338290" border="0" /></a><br />Each CLB has n-inputs and only one input, which can be either the registered or the unregistered LUT output. The output is selected using a 2x1 mux. The LUT output is registered using the flip-flop (generally D flip-flop). The clock is given to the flip-flop, using which the output is registered. In general, high fanout signals like clock signals are routed via special-purpose dedicated routing networks, they and other signals are managed separately.<br /><br />Routing channels are programmed to connect various CLBs. The connecting done according to the design. The CLBs are connected in such a way that logic of the design is achieved.<br /><br /><span style="font-weight: bold;">FPGA Programming</span><br /><br />The design is first coded in HDL (Verilog or VHDL), once the code is validated (simulated and synthesized). During synthesis, typically done using tools like Xilinx ISE, FPGA Advantage, etc, a technology-mapped net list is generated. The net list can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated is used to (re)configure the FPGA. Once the FPGA is (re)configured, it is tested. If there are any issues or modifications, the original HDL code will be modified and then entire process is repeated, and FPGA is reconfigured.Unknownnoreply@blogger.com1