Uncle Sam wants you to solve big scientific and engineering bottlenecks outside the hallowed walls of academia. On 14 May, the U.S. National Science Foundation (NSF) issued a solicitation inviting what it calls “X-Labs,” or independent research organizations, to apply for a total of US $1.5 billion over 10 years. The structure of the X-labs solicitation is new for the United States government and closely matches an emerging private funding model for what are known as focused-research organizations (FROs), which various think tanks and philanthropies have proposed and tested during the last six years.

A focused-research organization is a team of scientists, engineers, and other technology developers that works on a well-defined problem with a target duration of three to seven years and on a budget in the tens of millions of dollars. Some examples have sought to build an ultrasound-based brain-computer interface, quantify marine CO₂ removal, and improve formal verification in mathematics. The funding for these FROs required a team approach to science larger and more agile than a typical academic lab but with a more academic appetite for scientific risk than a commercial venture might have. In some ways, they echo work done by the Defense Advance Research Projects Agency (DARPA), which is known for helping bridge high-risk research and early-stage commercialization of many technologies.

“The NSF’s X-Labs announcement is a welcome signal that the global research community is serious about finding new ways to fund ambitious, high-risk science,” says Pippy James, deputy CEO of the Advanced Research + Invention Agency (ARIA), a United Kingdom government funding body in London that uses a similar model to the X-Labs.

The NSF’s first two X-Lab research areas are scientific instrumentation for sensing and imaging and interconnects and integrated photonics for quantum systems, and the solicitation says the agency will announce additional topics within weeks.

The funding is structured in phases, with $1.5 million per project in the first year, then up to $50 million per project over the next two to three years for selected projects, with a third, more open-ended phase after that. That first-year funding is more than seven times as much as for the typical NSF project of around $200,000.

“Compared to incremental, project-based grants, larger institutional grants and longer-horizon grants let teams take on harder, more infrastructure-heavy problems with the agility to pivot as they learn,” says Jenn Gustetic, director of metascience and R&D policy at the Institute for Progress (IFP), a Washington, D.C. think tank that made a proposal last year for how the U.S. government could support more independent research organizations.

The NSF solicitation also requires applicants to demonstrate “substantial” independence from any non-X-Lab institutions such as a university or company, which the NSF defined in part to mean the ability to make decisions on research direction, partnerships, and staff in days rather than weeks. It would be difficult for a full-time researcher at a university to qualify, for example, which opens the door to industry researchers or academics willing to take extended leave.

What should new money for science look like?

“People have been kind of wanting to do [focused research organizations] in a fairly bipartisan way since 2020,” says Adam Marblestone, an early proponent who now directs Convergent Research, a Cambridge, Mass., nonprofit that has spent almost $400 million building a dozen FROs. Some larger goal-directed, rather than principal-investigator-centered, funding has existed for decades in other federal agencies in the form of the Advanced Research Projects Agencies for defense, intelligence, energy, and most recently health. ARPA program managers often took a more hands-on and flexible approach than typical three-year National Institutes of Health (NIH) or NSF grant managers could. On 2 June, the IFP published an Atlas of Innovation comparing many different research funding structures.

The NSF announcement comes against a backdrop of administration requests for dramatic cuts to the agency’s budget, though Congress has generally appropriated stable amounts. NSF has, however, not disbursed all its appropriated funding, because the Trump administration has been feuding with many universities, accusing them of discrimination, and suing them. Most recently, NSF stopped new funding for several prominent universities, Nature reported. MIT’s president in May said that the university has won 10 percent less federal money than the previous year.

The big-ticket nature of the X-labs might make administrators and principal investigators at those universities worry about whether it will impact their own funding. “I don’t think it’s a zero-sum game,” says Erica Goldman, director of policy entrepreneurship at the Federation of American Scientists, a Washington, D.C. science-policy think tank, “but the way the timing of the announcements have come out and the rhetoric out there make it very hard to see that.”

“NSF X-Labs is structured to complement the existing system, not displace it—adding an independent institutional type alongside universities, national labs, small businesses and corporate R&D,” the IFP’s Gustetic says. The X-Labs annual sticker price represents less than 2 percent of the agency’s overall budget of $8.75 billion in 2026.

The emerging field of metascience, which investigates how best to do science, has been debating how governments should build the proper pipelines for converting blue-sky research into returns for all taxpayers. Metascientists differ over how FROs should fit into the research system. Some argue that governments can’t expect to apply the vaunted DARPA model to everything. Others write that FROs are a great idea and that the federal government already has a version of them in the form of the Department of Energy’s National Labs, which have spun off science platforms such as the Human Genome Project and the Protein Data Bank.

NSF media affairs head Mike England told IEEE Spectrum that “X-labs creates space and provides funding for new institutions to achieve breakthroughs in scientific discovery, research, and translation, and ultimately helps create new platform technologies.” In addition, on 27 May NSF requested information for a new funding idea adjacent to X-Labs it calls Tech Accelerators. These would use NSF money and accelerator expertise to fund and guide “deep-tech” commercialization efforts in agriculture, materials, ocean, and scientific instrumentation.

Other elements of government are also exploring how to incorporate the FRO funding model. In December 2025, U.S. Representative Josh Harder (D-Calif.) introduced a bill that would apply the X-labs model to the NIH. England says that NSF is having conversations with other government agencies about the model and welcomes more agencies to explore it.

“We don’t have great evidence comparing how different funding mechanisms perform—individual project grants, milestone-based contracts, prize challenges, etc.” Gustetic says. “X-Labs is a chance to actually learn something about which institutional designs work for which kinds of problems.”

Universities will likely have to adapt to the new model. Mid-career academics may well want to take time away from their university homes to participate in an X-Lab or other FRO project, says Monica Dus, director of the Office of National Laboratories at the University of Michigan and a holder of NSF grants. Institutions will need to figure out how to cover teaching duties in their absence and how to assess commercial experience for tenure or other internal promotions. “Universities should adapt to make sure the research does really reach the people it is meant for,” she says.

Academics may also need to change their approach to succeed, Convergent’s Marblestone says. “When we go to academics at Convergent, it takes a few conversations to plan it, because they don’t always know how they’d manage $50 million and a professional engineering team. You really need a CEO.”

I have been an application-specific IC (ASIC) designer for almost three decades. Over that time, I’ve moved through the full academic trajectory, from graduate student to full professor; later, I transitioned to industry after an unsuccessful stint at entrepreneurship. When I made the switch to the private sector in 2019, I began focusing on a critically important aspect of the electronic industry: silicon intellectual property.

As much as 80 percent of the physical area in today’s most advanced chips is occupied by blocks that aren’t made for specific products or even designed by the consumer-facing companies that built them. Instead, chipmakers draw heavily on established silicon IP from companies like Arm, Cadence, Rambus, Synopsys, and the company I work for, Silicon Creations.

Throughout my career, I’ve designed chips for very different purposes, including enabling the research program in my academic lab and expanding the IP portfolio of my company. When I joined Silicon Creations, I had no idea how differently the industry approaches IC design and encountered a steep learning curve. Initially, it seemed that much of my two decades of academic research and training did not directly translate to the role. I had to learn new skills and adopt a new mindset.

Today, demand for ASICs is rapidly growing, driven by the need for specialized chips in the automotive sector, AI applications, and more. By one market estimate, the ASIC market is expected to grow from US $23.4 billion to $38.8 billion by 2033, and the semiconductor industry as a whole is projected to hit $1 trillion by 2030. The industry needs more chip designers—but if you’re coming from an academic background as I did, there are a few things you’ll need to know.

Different goals lead to different strategies

The differences between industry and academe begin with a divergence in purpose. In academia, my primary objective was to generate new knowledge: to propose a novel circuit technique, validate an unconventional architecture, or explore the limits of performance in a given domain. A successful chip is one that demonstrates a concept. In industry, it is not nearly enough to prove that something can work. The goal is to ensure that it works reliably, repeatedly, and at scale. Success is measured not by novelty but by whether the silicon meets specifications, yields as expected in production, and supports a competitive product delivered on schedule.

This leads to a stark contrast in risk tolerance. Academic designs often deliberately push into unproven territory, where even partial success can yield valuable insight. In industry, however, we systematically minimize risk. The cost of failure makes first-time silicon success a central requirement—especially at advanced technology nodes, where the lithography masks used to transfer circuit designs onto silicon wafers alone can cost tens of millions of dollars. As a result, industry design flows are built around eliminating uncertainty through conservative margins, extensive validation, and careful reuse of proven solutions.

“Academia explores the design space, asking what is possible, while industry exploits it, determining what is viable at scale.”

This paradigm has existed since the 1970s, when application-specific chip design was established. However, the gulf between academia and industry has expanded since the mid-2010s, when FinFET technology, a 3D architecture using vertical “fins” of silicon, was widely adopted in industry. System designs are also becoming increasingly modular with the advent of chiplets. This fundamentally altered the economics and complexity of ASIC development, with design costs rising by almost an order of magnitude. Initiatives like Taiwan Semiconductor Manufacturing Co.’s University FinFET Program and new government-funded chip-design hubs now let some well-resourced universities design for more advanced architectures, but the technology is still out of reach for many academics.

What the industry-academia split means in practice

Consider a startup developing an ASIC. Its engineering team may have deep expertise in a particular algorithm, sensor interface, or system architecture, the features that define its competitive advantage. But it is unlikely to possess world-class expertise in every supporting function. Developing each of these blocks internally would require significant time, capital, and specialized talent. Doing so could delay market entry beyond the startup’s viability.

Even large semiconductor companies face similar constraints. Advanced-node development demands intense focus. Allocating a team to redesign a standard interface block that has already been implemented elsewhere may be difficult to justify when differentiation lies at the system level, such as an inference chip’s ability to speed up neural network computations. The time it takes to move a new chip from conception to market and risk mitigation, not self-sufficiency, govern most decisions about in-house development versus outsourcing.

The economics of advanced IC manufacturing reinforce this reality. When the development cost of a leading-edge chip reaches hundreds of millions of dollars, minimizing risk becomes a central design imperative.

In this context, silicon IP emerged as a practical solution. Similar to how software developers rely on preexisting libraries rather than writing every function from scratch, ASIC designers license predesigned, preverified silicon blocks—such as processor cores, memory interfaces, and security engines—from highly specialized IP vendors. These blocks can then be integrated into larger, increasingly complex systems.

Design scope, verification, and time horizons

With the use of silicon IP, industry is able to widen the scope of its designs. Academic efforts tend to focus on block-level innovation: a new analog-to-digital converter architecture or an ultralow-noise amplifier, for instance. These designs typically abstract away many of the complexities of bringing a chip to market, such as packaging constraints, long-term reliability, and manufacturing yield.

In industry, the focus shifts to system-level integration. Modern systems on chips, or SoCs, incorporate dozens or even hundreds of functional blocks. Managing signal integrity, timing, firmware interaction, and system-level validation becomes as critical as the design of any individual block.

Verification philosophy also diverges sharply. In academia, the goal of verification is to demonstrate that the concept works under nominal conditions, which may not always reflect how it would perform in real applications. Even if only a fraction of fabricated chips from a multiproject wafer operates correctly, the design may still be considered a success if it validates the underlying idea.

At my academic lab for instance, we used to receive 40 chips from a TSMC prototyping service and started testing them in batches of five. If the first five or 10 chips proved functional, we had already collected more than enough data for a publication. If some of them failed, we weren’t required to mention this when publishing the results.

In industry, verification is exhaustive, critical, and often dominates the development schedule. Failures are measured in parts per million, and even rare anomalies are carefully analyzed and documented to identify root causes and prevent recurrence. When I started at Silicon Creations, I was surprised by the level of detail and scrutiny designs face.

Differences in time horizons and economic constraints reinforce each of these contrasts. Academic projects operate on flexible timelines aligned with research and funding cycles. If I missed a deadline, I just had to wait for the next cycle. Industry projects are driven by fixed product schedules and market windows, frequently targeting costly leading-edge nodes to achieve competitive performance, power, and area efficiency. Missing a deadline can negate the value of an entire design and may have major financial consequences along the entire supply chain.

In essence, academia explores the design space, asking what is possible, while industry exploits it, determining what is viable at scale. Both are indispensable, but they operate under fundamentally different definitions of success. As ASIC complexity continues to grow, understanding both perspectives will be essential for the next generation of engineers navigating the evolving semiconductor landscape.

This article appears in the June 2026 print issue.

A practical introduction to phase noise concepts, explaining how oscillator instability affects RF systems and how phase noise is measured, analyzed, and reported.

What Attendees will Learn

1. What phase noise is and why it matters — Learn how real-world oscillators differ from ideal ones, why short-term frequency instability arises, and why phase variations typically have a much greater impact than amplitude variations on system performance.
2. How phase noise degrades system performance — Understand the most common effects of excessive phase noise: spectral regrowth, reciprocal mixing, and constellation rotation in digital communications.
3. How phase noise is measured and reported — Explore the spectrum analyzer method and the cross-correlation technique, understand single sideband (SSB) phase noise plots and spot noise tables.
4. What advanced phase noise measurements look like in practice — Discover additional measurement types including integrated phase noise, additive (residual) phase noise, pulsed signal phase noise, and amplitude noise.

Chipmakers are struggling to shrink the amount of area a transistor takes up, so researchers are trying to build layers of devices on top of each other. However, many experimental 3D chips rely on exotic materials and perform poorly compared with regular silicon devices. But researchers at the University of Illinois Urbana-Champaign have found a new way to build 3D circuits from silicon. The secret is a process that lets them roll multiple layers of nanometers-thin silicon onto a wafer at relatively low temperatures.

Today’s 3D microchips, such as the AMD MI300 series, stack prefabricated layers on top of each other and connect them with the help of metal pillars known as through-silicon vias. However, the challenge of properly aligning the connections between these layers limits how many links can be made and therefore how useful 3D stacking can be.

By contrast, in monolithic 3D chips, layers of devices are fabricated directly on top of each other. This enables alignment of these layers with nanometer-scale precision, and with orders of magnitude denser connectivity than today’s 3D chips.

However, experimental monolithic 3D chips require transistors and other devices in the upper layers to be fabricated at 400 °C or less to preserve the wiring that connects their components together. Such 3D chips have been made using a variety of materials, but their performance and reliability all proved much worse than the metal-oxide-semiconductor field-effect transistors (MOSFETs) found in virtually all conventional microchips, erasing most of the gains offered by a monolithic 3D design.

Now scientists have created monolithic 3D chips from silicon at less than 200 ℃. “For years, people assumed monolithic 3D would require exotic new materials such as carbon nanotubes, metal-oxide semiconductors, or 2D semiconductors,“ says Qing Cao, an associate professor of materials science and engineering at the University of Illinois Urbana-Champaign. “Demonstrating that silicon can do the job means this technology can plug directly into existing manufacturing ecosystems, which dramatically accelerates its path toward real impact.”

Low-temperature junctionless transistors

Instead of the MOSFETs used in most chips, the new 3D chips rely on junctionless transistors. Regular MOSFETs are made using both n-type semiconductors, which are doped to contain an excess of electrons, and p-type semiconductors, which are doped to produce a deficit of electrons. Charges enter a transistor through its source terminal, travel down a channel, and exit out the drain terminal. In MOSFETs, if the the source and drain are made of p-type silicon, the channel will be made of n-type, and vice versa. The p-n junctions where these semiconductor types meet interrupt the flow of current. When a gate electrode applies voltage to the channel, current can flow across.

Each layer of a new kind of 3D contains so-called junctionless transistors. The bottom layer is made from silicon with excess mobile electrons, the top from silicon with excess holes. The transistors are linked together vertically to form complementary logic.Bao Lam, Yung Man Yu, et al.

In contrast, in junctionless transistors, the source, channel and drain are all completely either p-type or n-type, and so operate without p-n junctions. When a voltage is applied to the gates, they switch on, allowing current to flow. First proposed in 1925, they were not built until 2010 due to limits in fabrication technology; they require highly and uniformly doped channels at most about 10 nanometers thick. In MOSFETs, chipmakers use high heat to make sure dopants are located precisely where they are needed to be in the silicon crystal to create p-n junctions. Junctionless transistors don’t need these high temperatures.

“Junctionless devices also use a simpler process flow, which can reduce costs and improve yield,” Cao says.

The new 3D chips are made by laying down uniformly doped single-crystal silicon membranes each 10 nm or less thick using a wafer-scale roll-transfer-printing process. “Because the membranes are so thin and flexible, they conform to the underlying surface, avoiding the voids and warpage that often plague wafer bonding between rigid wafers,” Cao says.

That the nano-membranes can transfer onto surfaces that are not necessarily perfectly flat “is important because the current method typically used in industry requires sub-1-nanometer roughness for the surfaces to be bonded together and extremely flat—only a few microns of variations across the wafer,” says Veeresh Deshpande, an associate professor of electrical engineering at the Indian Institute of Technology Bombay, who did not participate in this study. “The proposed method simplifies the process complexity and allows stacking several tiers of transistors, both for advanced computing and memory like DRAM.”

Cao and his colleagues fabricated three levels of junctionless transistors on a 75-millimeter silicon wafer, with each tier composed of 625 transistors over a 1,600-square-mm area. From these transistors they constructed a variety of logic gates and circuits—including inverters, NAND and NOR gates, and static random access memory (SRAM) cells—using vertical connections between the layers that were aligned with sub-10-nm accuracy.

The researchers were able to form circuits made up of transistors distributed over all three layers of the 3D chips. That led to a six-transistor SRAM cell with a footprint as little as one-third the size of its 2D layout.

A transistor’s switching speed depends on its current density, and the junctionless transistors showed a current density that could exceed 650 milliamperes per micrometer, which is comparable to older commercial silicon MOSFETs. More advanced MOSFETs do show current densities exceeding 1,000 mA per micrometer, but Cao and his colleagues say that future engineering could further improve the performance of their devices.

“The key implication is that vertical stacking may not have to come with a severe transistor-performance penalty,” says Saptarshi Das, a professor of engineering science and mechanics at Pennsylvania State University, who did not take part in this research. “If scalable, this could open a practical path to denser, more energy-efficient chips with much shorter interconnects.”

Roll-transfer processes

The silicon wafers Cao’s team used are much smaller than the 300-mm ones most fabs use today. But transferring and stacking silicon membranes even across a 75-mm wafer without cracks, wrinkles, or defects “required a series of engineering innovations,” Cao says. These included adding surfactants during certain etching steps to reduce surface tension; adding polymer support layers for mechanical stability and surface protection; and adopting a roll-lamination process to apply uniform pressure during transfer.

“We began in 2019,” Cao says. “By 2024, we realized we had solved the fundamental barriers. The following year and a half was spent refining the process and demonstrating multilayered devices at wafer scale and 3D logic circuits.”

Beyond computing, integrating silicon with other materials in monolithic 3D devices may open up new applications “that were previously out of reach.” Cao says. “For example, vertically stacking different types of single-crystalline semiconductors could enable ultrasensitive X-ray-detector panels or compact multispectral imaging systems.”

A new 3D chip has three layers of silicon transistors separated by about 90 nanometers of dielectric.Bao Lam, Yung Man Yu, et al.

One challenge monolithic devices will face is yield. “When you stack devices vertically, the traditional assumption is that every transistor in every layer must work perfectly, which can reduce overall chip yield,” Cao says. “We are working with circuit designers on defect-tolerant architectures that can absorb imperfections with minimal area and power overhead.”

Another hurdle is the way these 3D chips increase power density, concentrating heat. “We are collaborating with circuit and architecture teams on solutions such as dynamic voltage and frequency scaling and AI-assisted on-chip power regulation to actively manage heat,” Cao says.

Cao suggests the new approach is initially only promising for research and low-volume prototyping applications. “Once the benefits of monolithic 3D integration are clearly established, we can work toward high-volume manufacturing,” Cao says. “We simply want to be realistic and avoid over-claiming before the technology has been validated in those settings with full cost analysis.”

The scientists now want to partner with semiconductor foundries to demonstrate and refine the technology in a manufacturing environment, Cao says. Ultimately, “because our approach is silicon based and compatible with foundry processes, it has a realistic path to adoption,” he notes. “It will be especially valuable for AI workloads that are increasingly limited by communication bottlenecks, which is directly addressed by this technology by bringing compute layers physically closer together.”

Open-source software is ubiquitous: Linux is the dominant operating system on servers and supercomputers worldwide; Wordpress powers over 40 percent of all websites, among other major projects. Open-source hardware has existed since the late 1990s, but it hasn’t seen nearly the same level of interest or adoption as its software-focused cousin.

Dominic Rizzo, CEO and founder of the startup zeroRISC, aims to change that. Today, the nonprofit global security standards consortium GlobalPlatform launched Pavona, where Rizzo will be a governing board chair. The goal of Pavona is to facilitate the adoption of open hardware into all kinds of applications, including tiny IoT devices and massive data centers, by making the elements modular, standardized, and trusted.

Pavona is a new open-hardware ecosystem. It provides a starting kit of hardware modules, coupled with reference designs, a set of software tools to streamline adoption in different types of chips, and software tooling to ease integration. It also has a governance structure aimed at lowering the barrier to entry for adding new open-hardware designs and collaborating on development.

“I think it’s foundational,” says Andrew “bunnie” Huang, hacker and founder of Baochip, which is a founding member of Pavona. “We are now at the point where we finally have enough of a nugget of something open that we can spread it around. The outcome of this experiment is going to determine the shape of how we interact with hardware and open source for a long time.”

How open-source hardware differs from open-source software

The main reason open-source hardware hasn’t seen as much of a boom as software is almost too obvious to name: hardware needs to be manufactured, and manufacturing costs money. “Hardware, when it’s built, requires atoms,” Huang says, “which requires logistics and payment.”

At bottom, manufacturing itself is closed source. Because of this, open-sourcing hardware is inherently layered: While the chip fabrication, physical design kit, and foundry process remain closed, the layers on top of that, such as the design verification, system architecture, instruction-set architecture, and firmware, may be open source.

The Pavona ecosystem isn’t meant to deepen the penetration of open source through the layers. Instead, it’s meant to take the available open-source layers and facilitate their adoption and repurposing into as broad an application set as possible. “A lot of the work we’re putting into Pavona has to do with the infrastructure and the architecture that connects all this stuff together,” Rizzo says, “so it becomes much more like Legos, so you can use it in one configuration for a small IoT device and in another configuration for some large data-center system-on-a-chip.”

Part of making the hardware components more modular is software. Rizzo and his team built what they call an architectural composition engine that serves as a wrapper around the hardware, allowing it to interact with different types of computing cores, be they ARM or RISC-V. This way, a company can integrate the open hardware into their existing architecture without changing the software stack.

Pavona begins with security chip OpenTitan

Pavona’s starting kit of open-hardware designs includes components of OpenTitan, a chip that provides a “hardware root-of-trust,” a chip-level source of security that serves as a foundation for all secure operations in a computer. They also include extensions of the OpenTitan design that incorporate efficient cryptography that’s safe against possible future attacks from a large-scale quantum computer.

According to OpenTitan’s proponents, security hardware benefits from openness more than other chips, because if anyone can inspect and verify the design, and there is an active community of people stress-testing the hardware, it can become more trustworthy, and therefore more secure. It also makes the process of proving compliance with various regulatory requirements more straightforward.

Rizzo is counting on three factors to drive adoption of these open-security chips. The first is the AI boom, which has caused a massive increase in demand for chips of all kinds, not only the GPUs but also less well-known components like networking cards, monitors, and more. The second is the regulatory push toward transitioning to postquantum security, which both the U.S. and European governments have legislated to happen by the end of 2030. And third is new regulatory requirements in the European Cyber Resilience Act, which adds new security verification and reporting requirements for products sold in the European market.

“I think those three things together are all driving people in this direction of using secure, open-source silicon,” Rizzo says.

Security hardware may be just the beginning. Pavona is designed to make it as easy as possible to pull in new hardware modules. One need not be a paying member of Pavona to contribute new designs. “We absolutely are rejecting gatekeeping,” Rizzo says.

To increase trust from both individual contributors and large companies, Rizzo and his team developed a governance structure based on large open-source projects from the software world, such as Yocto. Contributing-member companies get representation on Pavona’s governing board. However, an independent technical committee makes the high-level technical decisions. This separation of managerial and technical oversight is meant to increase trust and transparency. “People get very discouraged when they feel like, ‘Hey, I made a contribution, and then someone made a decision in a hallway somewhere and told us later.’ So this is more consensus based, it’s more discussion based. And so those discussions have to be open,” Rizzo says.

Frank Nagle, the Linux Foundation’s advising chief economist and a research scientist at MIT, says compliance with standards and transparent governance are the keys to adoption of open-source technologies. “Having that type of structure in place will hopefully give it a fighting chance and allow it to reach scale, without people being concerned that it’s controlled by any one company.”

Pavona’s architectural-composition engine allows hardware to interact with different types of computing cores, so a company can integrate open hardware into its existing architecture without changing the software stack.Dominic Rizzo

The open-hardware future

Nagle argues that an underappreciated benefit of open source is that it allows private companies to work together, collaborating on core technology while still competing on specialized implementations.

“My favorite example of this I heard from a car manufacturer,” Nagle says. “The seat in your car has a little button that slides your seat backward and forward. Nobody’s buying one car rather than another car because that little toggle is better. But if you didn’t have one of those in your car, then somebody might not buy your car.”

Many technologies fall into the same category as the car seat’s button—technologies that are necessary but not a differentiator of the product. Security chips are a great example: Every piece of hardware needs security; however, few have it as their main function. These are the parts that benefit from open source, Nagle explains.

Collaborating on such hardware may enable cost savings for chip manufacturers and their customers, making the AI boom more economically sustainable.

Perhaps even more important, open sourcing some hardware development can lower the barrier to entry for new people to enter the field. To aid in this quest, Pavona also provides multiple “getting started” guides, software emulation tools, and FPGA code that anyone can download onto a board and get up and running in under 10 minutes.

“I want to get more people involved,” says bunnie Huang. “Particularly young people, particularly new people. Because we need a more robust ecosystem, more new ideas to ensure that we have the ability to maintain these technologies we depend upon.”

Darwesh Singh thinks Nvidia has a weakness.

The last decade of Nvidia’s history was among the most consequential stories in technology ever. The company’s stock price has increased over 200-fold since 2016, and deployed Nvidia AI compute capacity has surged to 225 times greater than the first quarter of 2021, according to data tracked by Epoch AI.

Yet Nvidia may in some ways be a victim of its own success. Its dominance in AI has led to GPU designs that prioritize tensor units and low precision math. These decisions make sense for AI, but less so for some creative, scientific, and industrial work.

Singh’s five-year-old startup, Bolt Graphics, sees an opportunity to build a GPU specifically for these use cases. Jill Mueller, Bolt’s chief marketing officer, puts it bluntly. Nvidia has “a fundamental lack of understanding of their customer,” she says. “They just throw stuff at you, and there you go.”

Bolt aims for this potential weak spot with Zeus, a GPU that will be sold as both a PCIe (peripheral component interconnect express) card for desktop workstations and, for those who require more performance, a rack-mountable server containing four Zeus GPUs (for up to 96 per rack).

While Nvidia goes low-precision, Bolt goes high

Jacob Feldgoise, senior data research analyst at Georgetown University’s Center for Security and Emerging Technology, has also noticed a shift in Nvidia’s recent hardware.

“AI is sucking the computational units used for high-precision workloads out of that hardware,” he says. “If you look at Nvidia’s highest performance GPUs, generation to generation, a greater share of the hardware has been allocated to low-precision compute, as opposed to high-precision compute, which is generally needed for scientific computing.”

Precision refers to how many bits a GPU uses to represent each number. High-precision formats like FP64 (64-bit floating point) preserve more digits and a wider range, while FP16 and INT8 sacrifice precision for speed. Recently, Nvidia introduced a new 4-bit number format, NVFP4, to accelerate AI workloads, which generally tolerate low-precision math.

But some tasks require precision. Singh cited geographical information systems, such as Esri’s ArcGIS, as an example. When rendering the planet on a GPU, low-precision arithmetic applied to large coordinate values can introduce errors that cause objects to drift.

Because Zeus, unlike so many other GPUs, is not designed primarily for AI, its design makes FP64-native vector cores a focus and allocates a large share of silicon to them.

“[Nvidia and AMD] make a conscious trade-off to allocate more die space to matrix multiplication and tensor units and less towards fixed function hardware,” Singh says. ”We decided to allocate the die space a bit differently.”

Rasterization is out, path tracing is in

A focus on FP64 isn’t the only way Bolt differs from the norm. Zeus is also built to render graphics with path tracing instead of rasterization.

Rasterization is the traditional method of high-performance 3D rendering. It projects 3D triangles onto a pixel grid and uses mathematical abstractions to determine the correct color for each pixel. Path tracing instead does the equivalent of shooting rays from a camera to simulate how light should bounce and interact. It delivers more accurate lighting but is computationally expensive.

As with high-precision math, Bolt believes it can find an edge by placing more emphasis on path tracing than do today’s GPUs. Rasterization is supported by Zeus but significantly scaled back; Singh estimates that Zeus’s raster performance is about half that of a comparable Nvidia card.

Bolt’s fresh arrival to the GPU arena also allows the company to take a clean sheet approach unburdened by legacy support. This differs from Nvidia and AMD, which must integrate path tracing alongside rasterization in a way that can support numerous existing applications and application programming interfaces (APIs).

Bolt claims that a server rack with 28 Zeus GPUs will deliver real-time path traced performance equivalent to 280 Nvidia RTX 5090 GPUs. The aim is for this configuration of Zeus hardware to support real-time path tracing that simulates up to 20 “bounces”—a reflection or collision of the simulated light—at 4K resolution and 30 frames per second. This is a high degree of accuracy required for professional rendering workloads; for comparison, even the most graphically attractive path traced games simulate just a few bounces.

Can a startup really launch a new GPU?

There’s a logic to Bolt’s approach. Nvidia and AMD are focused on AI, but GPUs are still useful for many tasks besides AI. However, Bolt will need to overcome two key technical hurdles.

The first is production. Cutting-edge silicon production is in short supply, and leaders like Nvidia have most leading-edge production capacity tied up. The Zeus GPU will instead be fabricated on TSMC’s older N5 process node. Bolt is betting that an older process node will keep Zeus competitive with Nvidia on price.

Bolt may also find it challenging to convince users that an unproven GPU is a safe bet. Driver support for software is always a headache in the GPU arena—just ask Intel—and the use cases that might benefit Zeus’s high precision and path tracing will also require reliable drivers.

Bolt plans to address this by launching with support only for specific applications. “We know that PC gaming is a huge segment,” Singh says. “But our approach is we want to target professional, creative, and high-performance compute first.” The company is working with software companies including Blender, Autodesk, and SideFX.

Discover how the ZEISS Crossbeam 750 FIBSEM sets a new benchmark for precise TEM lamella prep, tomography, and advanced nanofabrication. This delivers better resolution, better SNR, larger usable FOV, and shorter acquisition times. Learn how uninterrupted FIB milling will reduce damage and rework, accelerate time to TEM, and increase first pass success—so your FA, yield, and materials teams make faster, confident data driven decisions.

Join us to discover how the new ZEISS Crossbeam 750 with its see while you mill capability delivers precision and clarity—every time—for demanding FIB-SEM workflows. Designed for extremely challenging TEM lamella preparation, tomography, advanced nanofabrication, and APT‑ready lift‑out, Crossbeam 750 combines a new Gemini 4 SEM objective lens, a double deflector, and a next‑generation scan generator to elevate both image quality and process confidence. You’ll learn how better resolution and better SNR translate into more image detail and shorter acquisition times, while the low‑kV FIB performance enables more precise lamella prep.

We’ll demonstrate High Dynamic Range (HDR) Mill + SEM—an interwoven SEM/FIB scanning mode that suppresses FIB‑generated background. This enables immediate, clean visual feedback, even during nudging the FIB pattern live while milling . The result: confident endpointing with uninterrupted FIB milling and pristine, metrology‑grade surfaces with the lowest possible sample damage.

This session is ideal for semiconductor failure analysists, yield teams and materials scientists seeking faster time‑to‑TEM, higher first‑pass success, and consistent outcomes at low kV. See how Crossbeam 750 empowers you to make earlier stop‑milling decisions, cut rework, and reliably plan turnaround time—so you can move from sample to insight with confidence.

Register now for this free webinar!

Want to know what the next 10 years of Moore’s Law is going to look like? Maybe the next 15? The Belgium-based nanotech research institution Imec revealed its updated roadmap this week at its annual technology forum, ITF, and it points to a challenging road ahead for chip manufacturers.

The next evolution in CMOS transistors, the kind in almost all chips on the planet, will be the complementary field-effect transistor (CFET), and Imec predicts its commercial introduction will begin around 2033.

Imec's Roadmap

Imec’s new roadmap shows a change in the structure of transistors starting at the A7 node around 2033. Here’s a guide to reading the roadmap.

A7: What industry calls the “7 Angstrom” process node. It’s just a name; there’s not necessarily any structure in the transistor that is actually 7 Angstroms.

CPP: Contacted poly pitch is the shorthand for the distance in nanometers from one transistor to another.

Cell: Cell height is the smallest dimension of a logic cell in nanometers.

4.5T: The number of parallel interconnects (tracks) fitting within the smallest logic cell.

0.55NA EUV: EUV lithography using a higher numerical aperture (0.55), meaning it can print finer features than today’s 0.33NA machines.

MP: This is the minimum pitch, the distance from one line to another, that EUV can produce.

Further out, Imec expects another transition in transistor technology, this one driven more by power reduction than squeezing more devices onto a chip. In 2041, chipmakers may replace the main silicon part of the transistor, the channel region, with two-dimensional semiconductors. These are materials, such as molybdenum disulfide, that act as semiconductors even though they are only a single atomic layer thick.

Yes, 15 years is a very long time in an industry as fast moving as semiconductors. Imec’s projections extend so far out because of the role of its research in the semiconductor industry, says Paul Heremans, the organization’s chief technology officer. “Our research programs do de-risking of technology options,” he says. That is, they explore the costs and benefits of different choices with the aim of narrowing the field for chipmakers. “We have to be really well ahead of the time of the introduction of such technology into a real product, because after our de-risking work, there is still a lot of engineering and development work to get these technologies into production,” he says.

With de-risking as the goal, much of Imec’s focus right now is on what’s coming in 2033, and that’s the CFET.

So Many Choices for CFETs

The CFET is an attempt to build two transistors in the space of one. The CMOS logic that’s run computing for decades relies on two types of transistors—one called PMOS (p-channel metal-oxide semiconductor), the other NMOS (negative-channel metal-oxide semiconductor). They function so that the same input signal will cause one to switch on and the other to switch off, which helps foster relatively efficient operation. Today they are built in pairs side by side. CFETs would stack them on top of each other, which would be as good as halving the area of some circuits, according to proponents.

The likely path to the CFET builds both transistors at once, instead of one after another or building them on separate wafers and then somehow fusing them together. That starts by depositing multiple alternating layers of silicon and silicon-germanium onto a silicon wafer. After trenches and other features are carved through those layers, etchants that destroy silicon-germanium (but not silicon) are deployed to leave a set of suspended stack, nanometers-thick silicon ribbons. The top set of those ribbons, called nanosheets, become the PMOS transistor, and the bottom set becomes the NMOS, or vice versa.

RELATED: 3D-Stacked CMOS Takes Moore’s Law to New Heights

The world’s largest chipmakers—Intel, Samsung, and TSMC—are now working to make CFET-based chips manufacturable. Each of them have constructed prototype CFET chips. TSMC used its devices to build a super compact memory cell and a key test circuit called a ring oscillator, company engineers announced last December at the IEEE International Electron Devices Meeting. In June, at the IEEE VLSI Symposium, Samsung will detail a CFET that is simultaneously the smallest yet and made with the most layers of nanosheets (six in total).

RELATED: The Transistor of 2047: Expert Predictions

Nevertheless, how best to make CFETs is far from settled. “It is very clear that there are many versions still open,” Heremans says. For example, Imec has been developing new ways to better electrically separate the top and bottom transistor from each other, so they can work independently. The process that would make that possible is complicated. The silicon and silicon-germanium layers that will become the top transistor would be made on an entirely different silicon wafer. The two wafers are then bonded together in a way that leaves only the silicon and silicon-germanium layers from the top wafer attached to the bottom wafer. The process also leaves an extra layer of insulation between the material from the top wafer and the bottom wafer, providing the needed electrical isolation.

As difficult as that might seem, it could also help solve a mismatch in the speed of charge through PMOS and NMOS. Today’s chips use silicon wafers that are sliced along a crystal plane that favors conduction in NMOS. But if the PMOS layers are made on a separate wafer, that wafer could be cut to favor those devices. Intel is testing that scheme right now and will report the results of that work in June at the IEEE VLSI Symposium.

2D semiconductors in 15 years?

Imec expects CFETs to follow a similar evolution to other recent technology introductions, such as the FinFET (fin field-effect transistor) 15 years ago, and the nanosheet transistor, which is entering commercial products now. That is, an initial launch, then an effort to boost the density and performance, and finally a push to squeeze a bit more performance or power efficiency out of the dense version.

After that, probably around 2041, Imec expects industry to swap the silicon in CFETs for something new, such as one or more types of 2D semiconductors. Unlike with the move to CFETs, 2D semiconductors would mostly be about improving power consumption.

RELATED: 2D Transistors Could Come Sooner Than You Think

“The general goal of continuing the roadmap is, of course, to propose technologies that will increase the operation per watt that you can generate,” Heremans says. In advanced chips, a small reduction in voltage has an outsized effect on reducing power.

That’s where 2D could come in. 2D semiconductors are less than a nanometer thick, compared to the 3 nanometers of a future silicon nanosheet, Heremans points out. The transistor’s gate, which wraps around the channel region, could therefore use less voltage to control the flow of current through such a thin structure in comparison with the thicker silicon nanosheet. 2D CFETs could get a further efficiency boost if industry selects a semiconductor through which charge flows faster, Heremans suggests.

Interconnects, packaging, and CMOS 2.0

If CFETs arrive when Imec says they will, they’ll drop into an industry that’s already thinking in 3D. Intel has already moved power-delivering interconnects beneath the layer of silicon transistors on a chip, and with the CFET’s complicated connections, some data signals may have to move there as well.

Just as important, by 2033, chip companies will have more than a decade of experience stacking one chip atop another to increase the total amount of silicon in a processor. For example, in an AMD MI300 GPU, “compute tiles” made using the most advanced processes are stacked atop another die made using an older process that handles the GPU’s memory and communications.

The vertical connections in the AMD chip can be separated by as little as 9 micrometers. And that spacing is decreasing rapidly. “Today our most advanced wafer-to-wafer bonding technologies [in development] allow a pitch of about 200 nanometers,” Heremans says. “That means over 1 millimeter square, we’re talking about 25 million interconnects.”

RELATED: Hybrid Bonding Plays Starring Role in 3D Chips

That kind of density means that designers can start to build logic circuits in 3D dies,” Heremans says. Such an ability would lead to an evolution in chip design that Imec calls CMOS 2.0. In that scheme, not only can multiple chips made with different technologies be stacked together but individual chips can be made by fusing together layers of transistors, each optimized for a specific function such as memory density or driving current. “That gives you an enormous boost in what you can expect from this kind of fused chip,” he says.

This sponsored article is brought to you by Applied Materials.

At pivotal moments in history, progress has required more than individual brilliance. The most consequential breakthroughs — such as those achieved under the Human Genome Project — required a new operating paradigm: Concentrate the world’s best talent around a single mission, establish a common platform, share critical infrastructure, and collapse feedback loops. When stakes are high and timelines are compressed, sequential and siloed innovation simply cannot keep pace.

Today’s AI era is creating an engineering race with similar demands. Every company is pushing to deliver higher-performance AI systems, faster. But performance is no longer defined by compute alone. AI workloads are increasingly dominated by the movement of data: In many cases, moving bits consumes as much — or more — energy than compute itself. As a result, reducing energy per bit can extend system‑level performance alongside gains in peak compute.

The path to energy‑efficient AI therefore runs through system‑level engineering, spanning three tightly interconnected domains:

• Logic, where performance per watt depends on efficient transistor switching, low‑loss power, and signal delivery through dense wiring stacks.
• Memory, where surging bandwidth and capacity demands expose the memory wall, with processor capability advancing faster than memory access.
• Advanced packaging, where 3D integration, chiplet architectures, and high‑density interconnects bring compute and memory closer together — enabling system designs monolithic scaling can no longer sustain.

These domains can no longer be optimized independently. Gains in logic efficiency stall without sufficient memory bandwidth. Advances in memory bandwidth fall short if packaging cannot deliver proximity within thermal and mechanical constraints. Packaging, in turn, is constrained by the precision of both front‑end device fabrication and back‑end integration processes.

In the angstrom era, the hardest problems arise at the boundaries — between compute and memory in the package, front‑end and back‑end integration, and the tightly coupled process steps needed for precise 3D fabrication. And it is precisely this boundary‑driven complexity where the traditional innovation model breaks down.

The Traditional R&D Workflow Is Too Slow for Angstrom‑Era AI

For decades, the semiconductor industry’s R&D model has resembled a relay race. Capabilities are developed in one part of the ecosystem, handed off downstream through integration and manufacturing, evaluated by chip and system designers, and only then fed back for the next iteration. That model worked when progress was dominated by relatively modular steps that could be scaled independently and simply dropped into the manufacturing flow.

But the AI timeline has upended these rules. At angstrom‑scale dimensions, the physics enforces inescapable coupling across the entire stack: materials choices shape integration schemes; integration defines design rules; design rules dictate power delivery; wiring sets thermal budgets; and thermals ultimately constrain packaging scaling. System architects simply cannot wait 10–15 years for each major semiconductor technology inflection to mature.

Representing a roughly $5 billion investment, EPIC is the largest commitment to advanced semiconductor equipment R&D in U.S. history.

A long‑term perspective is essential to align materials innovation with emerging device architectures — and to develop the tools and processes required to integrate both with manufacturable precision. At Applied Materials, together with our customers, we are charting a course across the next 3–4 generations, extending as far as 10 years down the roadmap.

The angstrom era demands that we break down silos and bring together the industry’s best minds — from leading companies to leading academic institutions. If the problem is coupled, the solution must be coupled. If the timeline is compressed, the learning loop must be compressed. It’s not enough to just innovate — we must innovate how we innovate.

EPIC: A Center and Platform for High‑Velocity Co‑Innovation

This is the challenge that Applied Materials EPIC Center is designed to solve.

Representing a roughly US $5 billion investment, EPIC is the largest commitment to advanced semiconductor equipment R&D in U.S. history. When it opens in 2026, it will deliver state‑of‑the‑art cleanroom capabilities built from the ground up to shorten the path from early‑stage research to full‑scale manufacturing. But the facilities are only one component of the model. EPIC is also a platform, an operating system for high-velocity co‑innovation that revolutionizes how ideas move from the lab to the fab.

EPIC is a platform, an operating system for high-velocity co‑innovation that revolutionizes how ideas move from the lab to the fab.Applied Materials

The EPIC model compresses the traditional workflow. Customer engineers work side‑by‑side with Applied technologists from day one — moving beyond isolated process optimization and downstream handoffs. Within a shared, secure environment, EPIC tightly integrates atomistic modeling, test vehicles, process development, validation, and metrology feedback. Constraints that once surfaced late in development are identified and addressed early.

The result is a potentially 2x faster path that benefits the entire ecosystem under one roof:

• Chipmakers gain earlier access to Applied’s R&D portfolio, faster learning cycles, and accelerated transfer of next‑generation technologies into high‑volume manufacturing.
• Ecosystem partners gain earlier access to advanced manufacturing technology and collaboration opportunities that expand what is possible through materials innovation.
• Academic institutions gain opportunities to strengthen the lab‑to‑fab pipeline and help develop future semiconductor talent.

Building on decades of co‑development, we are reinventing the innovation pipeline with our partners across logic, memory, and advanced packaging to deliver the next leap in energy‑efficient AI.

Accelerating Advanced Logic

Logic remains the engine of AI compute. In the angstrom era, however, system‑level gains are increasingly constrained by power and energy. Extending AI performance now depends on architectures that deliver more performance per watt — accelerating the move to 3D devices such as gate‑all‑around (GAA) transistors, which boost density within a compact footprint while preserving power efficiency.

These architectural shifts are unfolding at unprecedented scale, with the logic roadmap already extending beyond first‑generation GAA toward more advanced designs. One key example is GAA with backside power delivery, which relocates thick power lines to the backside of the wafer, reducing resistive losses and freeing front‑side routing for tighter logic cell integration. Another example brings adjacent GAA PMOS and NMOS transistors closer together while inserting a dielectric isolation wall between them to minimize electrical interference. Further out, complementary FETs (CFETs) push density scaling even more by stacking PMOS and NMOS devices directly atop one another.

While these architectures deliver compelling gains in performance per watt and logic density without relying solely on tighter lithography, they significantly raise integration complexity. Manufacturing a single GAA device today can involve more than 2,000 tightly interdependent process steps. At the same time, wiring stacks continue to grow taller and denser to connect these advanced logic devices. Modern leading‑edge GPUs now in development pack more than 300 billion transistors into an area little larger than a postage stamp, interconnected by over 2,000 miles of wiring.

At this level of complexity, the process steps used to create these precise 3D devices and wiring stacks cannot be optimized independently. Design and process must evolve in lockstep, and materials innovation and fabrication methods must advance alongside device architecture. EPIC’s co‑innovation model is designed to accelerate exactly this convergence — enabling logic compute to continue advancing the frontiers of AI at the pace the roadmap demands.

Powering the Memory Roadmap

At the same time, the AI computing era is fundamentally reshaping how data is generated, moved, and processed — making memory technologies, especially DRAM, central to delivering the energy‑efficient performance AI systems require. As models grow larger and more data‑hungry, the DRAM roadmap is shifting toward architectures that deliver higher density, greater bandwidth, and faster access per watt.

At the DRAM cell level, this shift is driving a transition from 6F² buried‑channel array transistors (BCAT) to more compact 4F² architectures, which orient the transistor vertically to boost density and reduce chip area. Looking beyond 4F², sustaining gains in performance per watt will require moving past what 2D scaling alone can deliver. The industry is therefore turning to 3D DRAM, stacking memory cells vertically to add capacity within a constrained footprint. As these structures grow taller and aspect ratios intensify, high-mobility materials engineering in three dimensions becomes increasingly critical to performance and reliability.

Beyond the memory cell array, another powerful lever for DRAM scaling is shrinking the peripheral circuitry, which includes logic transistors and interconnect wiring. One emerging approach places select periphery functions beneath the DRAM array by bonding two wafers — one optimized for the DRAM cells and the other for CMOS logic — using multiple wiring layers.

In parallel, DRAM performance is being extended by leveraging logic‑proven enhancers in the memory periphery. These include mobility boosters such as embedded silicon germanium and stress films, along with wiring upgrades like improved low‑k dielectrics and advanced copper interconnects. Memory manufacturers are also transitioning periphery transistors from planar devices to FinFET architectures, following the logic roadmap to further improve I/O speed. These valuable inflections are central to EPIC’s mission — where they can be co-developed and rapidly validated for next‑generation memory systems.

Driving System Scaling With Advanced Packaging

As data movement becomes the dominant energy cost in AI systems, advanced packaging has emerged as a critical lever for improving system‑level efficiency—shortening interconnect distances, increasing bandwidth density, and reducing the power required to move data between logic and memory.

High‑bandwidth memory (HBM) marks a major inflection along this path. By stacking DRAM dies — scaling to 16 layers and beyond — and placing memory much closer to the processor, HBM enables rapid access to ever‑larger working datasets. This delivers step‑function gains in both bandwidth and energy efficiency.

More broadly, the rise of 3D packages such as HBM underscores why advanced packaging is becoming central to the AI era. Packaging now addresses system‑level constraints that logic and memory device scaling alone can no longer overcome. It also enables a move away from monolithic systems‑on‑chip toward chiplet‑based architectures, as AI workloads increasingly demand flexible designs that combine logic, memory, and specialized accelerators optimized for specific tasks.

A vital technology powering this roadmap is hybrid bonding. With interconnect pitches approaching those of on‑chip wiring, conventional bumps and microbumps run into fundamental limits in density, power, and signal integrity. Hybrid bonding removes these barriers by allowing dramatically higher interconnect and I/O density, supporting a broad range of chiplet architectures — from memory stacking to tighter compute‑memory integration.

As bonded structures like HBM stacks grow larger and more complex, warpage control, die placement, stack alignment, and thermal management become first‑order challenges. EPIC tackles these and other high‑value advanced‑packaging challenges through early, parallel co‑innovation across materials, integration, and manufacturing.

Bringing It All Together

Across logic, memory, and advanced packaging, our industry faces an ambitious roadmap that promises significant gains in energy efficiency for AI systems. But realizing that potential demands breakthrough materials innovation at a time when feature sizes are shrinking, interfaces are multiplying, and process interdependencies are escalating. These challenges cannot be solved on 10–15‑year timelines under the traditional relay‑race model. We must break down silos, align earlier across the ecosystem, and parallelize learning to keep pace with AI’s demands.

In the AI era, progress will be defined by the speed at which lightbulb moments turn into manufacturing and commercialization reality. The only viable path forward is a new innovation model — and EPIC is how we are driving it.

This sponsored article is brought to you by Ampace.

As AI workloads grow to gigascale levels, the global data center industry has hit a hidden physical wall. The real bottleneck is no longer just the thermal limit of the chip or the capacity of the cooling system — it is the dynamic resilience of the power chain.

Modern AI computing clusters, driven by massive GPU clusters, generate high-frequency, abrupt, and synchronized spikey pulse loads. As rack densities soar beyond 100 kW, these fluctuations are amplified into a “power paradox”: while the digital logic of AI is moving faster than ever, the physical infrastructure supporting it remains tethered to legacy response capabilities.

The power usage of these gigascale sites and their drastic, high frequency, abrupt load surges from the AI GPU clusters can trigger transient voltage events and frequency instability, risking the entire local grid. The grid itself is not robust enough to support these loads. This leads to the infrastructure gap: The utility is not robust enough and traditional backup sources, such as diesel generators and gas turbines, simply cannot react to millisecond-level power spikes in output. This will often force operators into a cycle of costly infrastructure over sizing just to buffer the volatility.

AI infrastructure requires energy systems capable of instantaneous response while safeguarding continuity and reliability.

The industry has explored various mitigations — from rack-level BBUs to 800V DC architectures — yet the mature, high volume, traditional UPS system remains the most viable and scalable foundation for gigawatt-level facilities. Consequently, the UPS-integrated battery system has emerged as the critical “physical buffer” to neutralize these pulses at the source.

At Data Center World 2026 in Washington, D.C., Ampace led a pivotal technical dialogue with Eaton during the session “Powering Giga-scale AI.” Their exchange unveiled a fundamental paradigm shift: To bridge the AI power gap, energy storage must evolve from a passive insurance policy into an active, high-speed stabilizer. By aligning Ampace’s semi-solid-state battery innovation with Eaton’s proven system intelligence, we are moving beyond simple backup to solve the physical paradox of the AI era.

To move beyond simple backup and solve the physical paradox of the AI era, Ampace is aligning its semi-solid-state battery innovation with Eaton’s proven system intelligence.Ampace

The “Shock Absorber” physics: semi-solid chemistry for AI pulses

Conventional power systems were designed for steady-state loads, not the rapid heartbeat of a massive AI GPU cluster. When thousands of GPUs synchronize their computing cycles, they generate high-frequency, abrupt pulse loads that can lead to voltage sags, frequency oscillations, and potential interruptions of critical AI training.

Ampace’s PU Series semi-solid and low-electrolyte cells address this challenge by acting as high-speed “shock absorbers.” Leveraging ultra-low internal resistance (DCR) and high cycle capability, these batteries neutralize millisecond-level power spikes at the source, stabilizing the local power loop before disturbances propagate upstream to the grid or on-site generators. These high-rate cells enable 100 kW+ racks to maintain peak performance without transmitting instability across the power chain.

This capability aligns closely with Eaton’s matured UPS architectures, such as double-conversion topologies and advanced power electronics upgrades, which have long prioritized rapid load responsiveness and high system stability.

Together, these approaches embody a shared industry philosophy: AI infrastructure requires energy systems capable of instantaneous response while safeguarding continuity and reliability.

Ampace’s semi-solid state chemistry minimizes liquid electrolyte, greatly reducing the risk of leakage and thermal runaway under continuous AI high-load conditions.Ampace

Algorithmic intelligence: synchronizing energy and control

Hardware alone cannot solve the AI power paradox; the system also requires intelligent coordination between energy storage and power management. Sophisticated battery management systems (BMS) like Ampace’s high-precision design track state-of-charge (SOC) with high-speed sampling, even during rapid, shallow cycling typical in AI workloads.

Complementary algorithmic approaches in modern UPS platforms — such as ramp-rate control and average power management — effectively suppress sub-synchronous oscillations and optimize load smoothing. In large-scale AI training environments, where thousands of GPUs can trigger millisecond-level power pulses, these intelligent layers ensure that batteries buffer high-frequency fluctuations without compromising the mandatory emergency backup reserves.

By transforming energy storage from passive “standby insurance” into active, schedulable assets, the system simultaneously safeguards continuous AI training and maintains the long-term health of the data center infrastructure. In practical terms, this means that even during peak compute bursts, the infrastructure remains stable, training cycles continue uninterrupted, and operators avoid costly oversizing or grid stress.

Eaton’s dual-layer algorithms serve as a valuable benchmark in this space, demonstrating how advanced control logic can achieve similar objectives, reinforcing Ampace’s approach and philosophy within the broader data center power ecosystem.

Economic scalability: optimizing AI infrastructure efficiently

One of the largest costs in deploying AI infrastructure is “oversizing”: procuring transformers, generators, and UPS systems to handle brief peak spikes. This traditional approach inflates the Total Cost of Ownership (TCO) and leads to wasted capital on underutilized hardware.

Ampace’s turn-key cabinet design developed by its independent R&D is engineered for seamless compatibility with mature, high volume UPS systems. By leveraging Eaton’s double-conversion UPS topologies alongside intelligent ramp-rate and average power management algorithms, AI data centers can scale dynamically without requiring costly infrastructure redesigns. This approach allows the UPS and batteries to act as active load-shapers, smoothing AI-driven pulses while strictly maintaining mandatory emergency backup capacity.

By utilizing energy storage as an active, schedulable asset, operators can right-size their infrastructure, avoid unnecessary grid upgrades, and deploy gigascale AI clusters with unprecedented efficiency.

Safety First: Protecting AI Infrastructure While Enabling Innovation

In high-density AI facilities, safety is non-negotiable. Ampace’s semi-solid state chemistry minimizes liquid electrolyte, greatly reducing the risk of leakage and thermal runaway under continuous AI high-load conditions.

Ampace’s turn-key cabinet design developed by its independent R&D is engineered for seamless compatibility with mature, high volume UPS systems. Ampace

At the same time, Eaton’s UPS design emphasizes system-level energy scheduling that never sacrifices mandatory emergency backup reserves, ensuring thermal safety and uninterrupted operation.

This “safety-first” approach ensures that infrastructure can sustain aggressive performance targets without compromising the physical integrity of the facility. Coupled with over a decade of proven high-cycle life operation and design under shallow pulse conditions, these systems can extend operational lifespan, reduce replacement requirements, and provide operators with confidence that safety and reliability remain uncompromised as compute density continues to grow.

To remain the scalable backbone of AI data centers

As AI computing scales over the next two to three years, the industry will face stricter grid requirements and even more demanding pulse load characteristics. This evolution demands a forward-looking design philosophy that harmonizes UPS, battery, and grid compatibility.

Ampace views current low-electrolyte semi-solid technologies as the optimal transitional step toward a fully solid-state future — one that promises ultimate safety and performance.

Ampace remains committed to this long-term technological roadmap. We view current low-electrolyte semi-solid technologies as the optimal transitional step toward a fully solid-state future — one that promises ultimate safety and performance. Whether through rack-level BBU, integrated UPS systems, or containerized storage, the universal core of the AI era remains constant: high-speed response, long shallow-cycle life, and refined energy management.

By engaging in deep technical exchanges with Eaton and leading energy innovators, Ampace ensures that its solutions not only meet today’s AI pulse challenges but also harmonize with broader infrastructure strategies and shared industry best practices.

Ultimately, as traditional diesel generators gradually give way to diversified alternatives, the integrated UPS-plus-energy-storage system will become the fundamental infrastructure standard.

The dialogue has just begun. Ampace will continue to engage in strategic exchanges with global industrial automation leaders and digital energy pioneers, co-authoring the playbook for a safer, more efficient, and more resilient AI-ready world.

When Mitchell Hsing was a grad student at MIT, he and his classmates were doing cutting-edge things using what was essentially chip-industry cast-off equipment. Just imagine what could get done if everyone had their own small fabs to spin up prototypes or manufacture small batches of chips, he thought. The result is InchFab, a startup selling a $5 million to $15 million shipping-container-size clean-room system that can do just about everything a not-so-advanced fab can. The compact size comes as a result of InchFab using much smaller silicon wafers than today’s multibillion dollar fabs do. Smaller wafers means fab equipment can be much smaller and way cheaper. InchFab now has customers all around the world, especially in places where people are looking to train up a chipmaking workforce ahead of planned new fabs.

Where did the idea for InchFab come from?

Mitchell Hsing: It really came from our own issues that we had trying to get chips made at MIT. MIT is arguably one of the best places in the world to do microfabrication-related research, and we were still using equipment from the 1980s that literally needed a floppy disc just to make it work.

Inchfab really kind of grew out of that frustration. In Martin Schmidt’s group, where I was at the time, we were looking at how we solve the problem of lowering the barrier of entry to microfabrication.

The solution was scaling down the size of the existing chip-processing equipment. As a result of that, you could scale the price of the equipment as well. My cofounders and I looked at how the physics and the chemistry changes when you go from, say, a large, conventional 50-gallon-oil-drum-size plasma vacuum chamber to something that’s the size of a 1-liter soda bottle.

How small are the wafers you designed the equipment to work with?

Hsing: In the very beginning, the project was called “One Inch Fab.” It wasn’t just a code name, there’s some reason behind it: The field of view of a stepper [a common photolithography tool], is about an inch by an inch. But we realized that there are many problems with 1-inch wafers. The first is that you can’t buy them, so you have to cut them out yourself, and there’s lots of problems with that. So then we quickly scaled to two inches, and now we’re actually at four inches [about 100 millimeters].

Is the physics different when you’re dealing with a much smaller substrate?

Hsing: The primary differences are on the plasma-based tools, and it’s not the substrate itself that dictates the changes. It’s the size of the plasma chamber. In plasma-based equipment, you have something called a sheath. It’s basically a layer of plasma along the chamber wall protecting the machine from killing itself. That sheath scales with the surface area of the chamber. When you go smaller, the surface area starts to become more prominent over the volume.

Was anything inherently easier when you shrunk it down?

Hsing: Some things come easier—the equipment that you need on the back end, like vacuum pumps, mass-flow controllers, valves, and things like that. Controlling a smaller volume is easier.

What can InchFab do and what can’t it do compared to a regular fab.

Workforce development is one of the big uses of InchFab’s fab-in-a-box.InchFab

Hsing: Our fab has the same process capabilities any other fab in the world would, including lithography, metrology, dry etch, plasma-enhanced chemical vapor deposition processes, atomic-layer deposition, and wet processes. Basically, you name the process, we likely have the process.

Our primary limitation is lithography, in terms of feature size and speed. Feature size scales with the speed, and the speed is important for manufacturing purposes. We could do half micron feature size using photolithography in some production volume. We could go down even smaller, to tens of nanometers. However, the write times are a lot slower, because you’re looking at electron-beam capabilities or imprint lithography.

When you first told me about this idea years ago, I didn’t believe it was possible. What were some of the early reactions to this effort, and what do you say in response to the naysayers?

Hsing: Oh yeah, we still get naysayers. The primary push back we get is that we need to be on large wafer sizes. The argument is: “If I produce on a larger wafer size, I could make more stuff per wafer. And as a result of that, the price per chip comes down.” That argument holds true if you could fill a fab running 10,000 wafers a month.

But what we have shown is that that doesn’t actually make sense. You need to be producing on a wafer size and a fab throughput that matches the markets you’re serving. That’s ultimately what dictates the price per chip. It’s the capital efficiency and utilization of your fab. Those two things have to match, not your wafer size. That’s what we’ve been able to show through the seven years that we’ve been running. Oftentimes [with our smaller wafers] we can be price competitive with an 8-inch foundry today.

What sort of customer can be price competitive in that scenario?

Hsing: It depends, but in general terms the largest markets that we serve today are industrial, sensing, biomedical, aerospace, and defense. We are branching into other areas right now as well, such as compound semiconductors and the whole slew of products and processes that come with that like power and high-frequency RF applications. And then right beyond that, we’re looking at the quantum and photonic space as well. Anything that requires a custom process flow or where the product volumes are not high to begin with is a good fit for us.

Let me just add another point regarding what our fabs are used for. A large part of our business right now is in workforce development. Nowadays everybody in the world pretty much wants to have some type of domestic semiconductor manufacturing capability. And there’s no better way, no cheaper way, to start it than with something like an InchFab. A lot of these countries are trying to build a large, 8-inch or 12-inch fab, which takes five years to build. But they could get started within the first five years with an InchFab. Even more importantly, once they build that fab, they’ll need a trained workforce to go run it. So we actually supply a fab line with a training course. These courses are modeled after the MIT courses that I took, but I designed them such that the student actually tunes all the recipes themselves. They make all the mistakes themselves. That’s how you learn.

Where do you expect InchFab to be five years from now?

Hsing: Really what we set out to do, is to democratize fabrication—to lower the barrier of entry, to enable everybody to be able to manufacture, or at least to play. I would say that what is limiting innovation on the microscale today is people’s access to microfabrication capabilities. I guarantee you, that if you give people these capabilities, they will figure some [stuff] out that people have never thought of before.

A guide to ten technological components — from THz communications and AI/ML to reconfigurable intelligent surfaces — poised to define 6G wireless networks.

What Attendees will Learn

1. Which frequencies 6G will use — Understand why THz bands (above 100 GHz) and the7–24 GHz range are under consideration, what challenges CMOS technology faces at sub-THz frequencies, and how new semiconductor approaches aim to close the output-power gap for future link budgets.
2. How AI/ML and joint communications and sensing reshape the air interface — how auto encoder-based end-to-end learning can replace traditional signal-processing blocks, and how a single waveform may serve both data transmission and radar-like environmental sensing.
3. What reconfigurable intelligent surfaces and photonics bring to the radio environment— Explore how programmable metamaterial panels can steer and shape electromagnetic waves, and how visible light communications and all-photonics networks extend capacity and lower latency.
4. How ultra-massive MIMO, full-duplex, and new network topologies enable a true 3D“network of networks” — Understand how antenna arrays with vastly more elements, simultaneously transmit/receive on the same frequency, and non-terrestrial nodes converge to deliver ubiquitous, high-capacity 6G coverage.

When things go bad—be it beer, batteries, or blood—they generate a certain class of molecules called free radicals. Scientists use a technique called electron paramagnetic resonance (EPR) spectroscopy to pick up the concentration and identities of free radicals, but today’s equipment relies on huge, heavy magnets.

Groups of researchers in California, Germany, and now France have been inventing ways to shrink the whole spectroscopy system onto a chip, so scientists can take the instrument into the field.

The most recent entrant in this space is a group of engineers at the French government technology labs CEA-Leti and CEA-IRIG, in Grenoble. They presented a new, potentially faster, take on chip-scale EPR earlier this year at the IEEE International Solid-State Circuits Conference in San Francisco. But competing research groups have also been working to speed these systems up, moving the process toward supersensitive real-time results.

Free Radicals and EPR

Chemicals are most stable when all the electrons in the outer orbitals of their constituent molecules are paired up, with each electron in the pair having an oppositely oriented property called spin. Free radicals are molecules with unpaired electrons, which makes them highly reactive. This can be good when it’s part of a necessary bit of biochemistry, or bad when it degrades materials, foods, or your body. (Free radicals are why we need antioxidants in our diet.)

“Free radicals determine the quality of almost everything on the planet,” says Jens Anders, director of the Institute of Smart Sensors at the University of Stuttgart, in Germany. Anders is considered by at least one expert as “one of the O.G.s” of chip-scale EPR for having pioneered the portable tech about a decade ago.

RELATED: Listen to Protons for Less Than $100

That “almost everything” includes technology, says Jean-Baptiste David, who led the work at CEA-Leti. “In a battery, the free radicals will reduce the capacity of the battery. In photovoltaic panels, it leads to aging,” he says.

EPR spectroscopy works because free radicals are paramagnetic. That is, their free electron spins will align with the magnetic field. In a full-size EPR machine, the sample under examination is placed between two poles of a powerful electromagnet, aligning the spins of the unpaired electrons. Then a weaker oscillating magnetic field is applied atop it.

This oscillation can come in two forms. In one form, called continuous wave EPR, the oscillating frequency conventionally is held steady, and the stronger field is swept through a range of values, necessitating a bulky specialized electromagnet. Through some creative circuitry, chip-scale EPR reverses this setup—using a simple magnet to create an unchanging field and sweeping through a band of oscillation frequencies. (Most EPR chips use frequencies in the satellite downlink X and Ku bands.) The spins of unpaired electrons will resonate with some of these frequencies. The EPR spectrometer’s circuitry picks this up and plots it as a frequency spectrum that chemists can interpret.

The 4.4-square-millimeter EPR chip is shown on a circuit board that fits between portable magnets.Jean-Baptiste David/CEA

Continuous-Wave Electron Paramagnetic Resonance

The CEA-Leti team’s chip uses the continuous wave method, but “we use a completely different way to measure the EPR phenomenon,” says David. By sweeping very quickly, the new circuit cuts the time the process takes while remaining sensitive enough to detect micromolar quantities of free radicals in a sample that’s just 10 nanoliters.

This first EPR chip, developed by Anders and his colleagues at Stuttgart about a decade ago, worked using the continuous wave method. It relied on a voltage-controlled oscillator—a circuit that outputs a signal with a frequency proportional to the magnitude of an input voltage—with an inductor that delivers the sweeping-frequency magnetic field to a droplet of beer or whatever you’re analyzing. When the frequency resonates with the free radicals’ electron spins, those spins couple with the inductor, altering the frequency of the oscillator, which is detected via a feedback loop.

Most EPR chips that came after work on essentially the same principle. According to CEA-Leti’s David, the feedback loop places a limit on how quickly the EPR chip can sweep through its range of frequencies. Speed is important, he says, because lingering too long on a frequency drowns out the response and long sweeps keep EPR from catching fast changes in free-radical concentration.

Hoping to speed things along, the CEA-Leti team came up with a different way of sensing spins. The new method, called injection-locked phase detection, is designed to sweep through its bandwidth in just 200 nanoseconds, equivalent to 1,400 terahertz per second. That’s three times as fast as competing systems, the researchers claim.

The new method relies on circuits called injection-locked oscillators (ILOs). Here, two oscillators are running at close to but not identical frequencies. One signal is “injected” into the other oscillator, forcing the latter to adopt the injected frequency. (Imagine two pendulum clocks on the same mantlepiece synching up with each other because of subtle vibrations sent through the shared surface.)

The team took advantage of the phase difference between the two oscillations to turn the ILO into a kind of frequency-to-phase converter circuit. The ILO connects to the inductor where the free radicals sit, and the frequency is swept both with the external magnetic field on and without it. The two resulting signals are subtracted from each other to deliver the pure EPR signal—no speed-limiting feedback loop needed.

EPR spectrometers usually rely on huge electromagnets.Jean-Baptiste David/CEA

Pulse Electron Paramagnetic Resonance

While the CEA-Leti development advances continuous wave EPR, other researchers have been focusing on chips that do a different form of EPR, called pulse mode. In pulse EPR, instead of presenting the free radicals with a sweep of frequencies, they’re exposed to a pulse containing a band of frequencies surrounding the central oscillation frequency. It’s like striking a bell. The spins all react at once but stop “ringing” in different ways. A computer can then tease out the frequency spectrum from this response. At ISSCC 2024, Constantine Sideris and his student Ray Sun at the University of Southern California presented the first chip that can actually perform both.

By using multiple pulses in a sequence, chemists can study additional properties of radicals that are difficult to see with continuous-wave EPR, says Sideris, who recently moved to Stanford University. “With a single pulse, you can excite a wide spectrum. You can look at a big bandwidth without having to sweep [through a band of frequencies] in the first place.”

Stuttgart’s Anders, too, has turned to pulse-mode EPR, and is launching a startup this summer, called SpinMagIC, to commercialize the tech. The first application will be checking the quality of food and especially, as the company is in Germany, beer. But eventually, the company will tackle cancer detection and other health-care issues.

Turning EPR chips into a product has meant solving a number of problems. Notably, the size of the coil that delivers the varying magnetic field had to be increased to accommodate larger volumes. That required segmenting the coil and inserting electronics within it to keep it from radiating its energy away like an antenna. “That was really the most important patent for the company, because now we have a chip with a coil that’s 2 millimeters across instead of 200 micrometers,” Anders says.

Meanwhile, the CEA-Leti and CEA-IRIG team plans to let loose its new version of EPR on scientific questions. The hope is that scientists “can start to see new phenomena, for example, that were not observed due to the speed of the technique,” says David.

Think one GPU is very much like another? Think again. It turns out that there’s surprising variability in the performance delivered by chips of the same model. That can make getting your money’s worth by renting time on a GPU from a cloud provider a real roll of the dice, according to research from the College of William & Mary, Jefferson Lab, and Silicon Data.

“It’s called the silicon lottery,” says Carmen Li, founder and CEO of Silicon Data, which tracks GPU rental prices and benchmarks cloud-computing performance.

The silicon lottery’s existence has been known since at least 2022, when researchers at the University of Wisconsin tied it to variations in the performance of GPU-dependent supercomputers. Li and her colleagues figured that the effect would be even more pronounced for AI cloud customers.

Performance varies for GPU models in the cloud

So they ran 6,800 instances of the index firm’s benchmark test on 3,500 randomly selected GPUs operated by 11 cloud-computing providers. The 3,500 GPUs comprised 11 models of Nvidia GPU, the most advanced being the Nvidia H200 SXM. (The team wasn’t just picking on Nvidia; the GPU giant makes up most of the rental cloud market.)

The benchmark, called SiliconMark, is intended to provide a snapshot of a GPU’s ability to run large language models, or LLMs. It tests 16-bit floating-point computing performance, measured in trillions of operations per second, and a GPU’s internal-memory bandwidth, measured in gigabytes per second. The results showed that the computing performance varied for all models, but for the 259 H100 PCIe GPUs it differed by as much as 34.5 percent, and the memory bandwidth of the 253 H200 SXM GPUs varied by as much as 38 percent.

Differences in how the GPU is cooled, how cloud operators configure their computers, and how much use the chip has seen can all contribute to variations in performance of otherwise identical chips. But Silicon Data’s analysis showed that the real culprit was variations in the chips themselves, likely due to manufacturing issues.

Such randomness has real dollars-and-cents consequences, the researchers argue, because there’s a chance that a pricier, more advanced GPU won’t deliver better performance than an older model chip.

So what should GPU renters do? “The most practical approach is to benchmark the actual rental they receive,” says Jason Cornick, head of infrastructure at Silicon Data. “Running a benchmark tool [such as SiliconMark] allows them to compare their specific instance’s performance against a broader corpus of data.”

In 2020, researchers fine-tuned a GPT-2 model to design fragments of logic circuits; in 2023, researchers used GPT-4 to help design an 8-bit processor with a novel instruction set; by 2024, a variety of LLMs could design and test chips with basic functionality, like dice rolls (though often these were flawed).

Now Verkor.io, an AI chip design startup, claims a bigger milestone: a RISC-V CPU core designed entirely by an agentic AI system. The CPU, dubbed VerCore, has a clock speed of 1.5 gigahertz and performance similar to a 2011-era laptop CPU.

Suresh Krishna, cofounder at Verkor.io, says the team’s key claim is that this approach is more effective than using only specialized AI systems for specialized tasks within the overall design process. “ What we learned is that the better approach is to let the AI agent solve the whole problem,” he says.

Bringing Human Workflows to Agentic AI

Verkor.io’s agentic system is called Design Conductor, and it’s not itself an AI model. It’s a harness for large language models (LLMs). A harness is software that forces an AI agent to proceed through structured steps. In this case, the steps are like those a team of human chip architects would follow: design, implementation, testing, and so on. The harness also manages subagents and a database of related files.

That means it can work autonomously with only an initial prompt—in this case a 219-word design specification—from the user. (The prompt is published in the Design Conductor paper.) It outputs a Graphic Design System II (GDSII) file, which can be used in existing electronic design automation (EDA) software.

Synopsys and Cadence, two major players in EDA software, also have agentic AI tools. These allow chip architects to automate some tasks with AI agents. Design Conductor is different because it’s built to handle chip design from spec to completion with full autonomy, something major EDA companies have not yet touted.

Ravi Krishna, founding engineer at Verkor.io, says Design Conductor’s workflow is “mirrored after the traditional process a human engineer might use.” It analyzes the specification, then writes and debugs a register-transfer level, or RTL, file (an abstraction of the CPU’s data flow) before iterating through subtasks like power delivery, signal timings, and layout, which are again checked against the specification. Some tasks, like layout, call tools to assist the agent. “It’s an iterative system.”

The system took 12 hours to create the VerCore design. That’s not long, but, because it uses AI agents, you might imagine it taking more or less time based on the number of agents thrown at it. However, Ravi Krishna says it’s not that simple, because some design tasks aren’t easily parallelized.

However, the general improvement of AI models over time has proven essential. “I remember that around the middle of last year, we tried to build a floating-point multiplier with the models of that time. It was slightly beyond what they could do,” says Ravi Krishna. VerCore—designed in December 2025— represents an increase in capability since then. “If it can’t do it today, it’ll do it in six months,” he says. “I don’t know if that’s a scary thing or a good thing.”

A First for AI Chip Design

VerCore uses the RISC-V instruction set architecture (ISA), a popular open-standard ISA that’s beginning to break out of niche applications, like storage controllers, into systems on a chip (SoCs) that can power laptops or smartphones. The CPU’s exact clock speed is 1.48 GHz and it achieved a score of 3,261 on the CoreMark processor core benchmark.

Verkor says this puts VerCore’s performance in line with the CPU core performance of Intel’s Celeron SU2300. Whether that sounds impressive depends on your perspective. The Celeron SU2300, which arrived in 2011, uses Intel’s Penryn CPU architecture, which debuted in November of 2007.

In other words, VerCore is no threat to leading-edge CPUs, but it’s notable for two reasons.

VerCore is the first RISC-V CPU core designed by an AI agent. Previous examples of AI chip design presented portions of a design but didn’t present a complete core. Ravi Krishna says the company wanted to target a design that an AI agent hadn’t previously accomplished. “From the perspective of trying to push the limits of what AI models can do, that was interesting to us,” he says.

And while VerCore’s theoretical performance has limits, it’s enough to suggest the design could be useful. Indeed, RISC-V is popular because it provides an ISA that’s free to use (RISC-V is an open standard). RISC-V chips generally aren’t as quick as their x86 and Arm peers, but they’re less expensive.

There’s one final caveat worth mentioning; the chip has not been physically produced. VerCore was verified in simulation with Spike, the reference RISC-V ISA simulator, and laid out using the open-source ASAP7 PDK, an academic design kit that simulates a 7-nanometer production node. Both tools are commonly used for RISC-V design. VerCore says its CPU can run a variant of uCLinux in simulation.

Skeptics will have a chance to judge for themselves. Verkor.io plans to release design files at the end of April. This will include the VerCore CPU and several other designs recently completed by the AI agent system. Verkor also plans to show an FPGA implementation of VerCore at DAC, the leading electronic design automation conference.

Should Chip Designers Worry about AI Agents Taking Their Jobs?

An AI chip designer that can bang out a CPU in 12 hours might seem like troubling news for flesh-and-blood engineers, but Design Conductor has its limitations. The team at Verkor.io say that despite improvements, LLMs still lack the intuition a human can bring.

Design Conductor can fall down rabbit holes that a human engineer would avoid. In one instance the agent made a mistake in timing, meaning that data was not moved across the CPU in agreement with its clock cycle. The model didn’t recognize the cause and made broad changes while hunting for the fix. It did eventually find a fix, but only after reaching many dead ends. “Basically, we are trading off experience for compute,” says David Chin, vice president of engineering at the startup.

Suresh Krishna concurs and adds that Design Conductor’s brute-force approach is likely to become less efficient as agentic systems tackle more complex designs. “It’s a nonlinear design space, so the compute grows very quickly,” he says. “As a practical matter, expert guidance and common sense helps a lot.”

Despite such issues, agentic systems like Design Conductor might accelerate chip design by accelerating iteration. They may also make design accessible to small teams that otherwise lack the resources or head count to pull off a project.

“It’s not at the point where you can have one person. I would say you still need five to ten, all experts in different areas,” says Ravi Krishna. “That team could get you to [a production-ready chip design] at this point.”

Photonic devices, which rely on light instead of electricity, have the potential to be faster and more energy efficient than today’s electronics. They also present a unique opportunity to develop devices using soft materials, such as polymers and gels, which are poor conductors of electricity but are easier to manufacture and more environmentally friendly. The development of these potentially squishy, flexible photonics, however, requires the ability to manipulate light using only light, not electricity.

In soft matter, that’s been done primarily by changing the physical properties of optical materials or by using intense light pulses to change the direction of light. Now, an international team of scientists has developed a new way of controlling light with light using very low light intensities and without changing any of the physical properties of materials.

Igor Muševič, a professor of physics at the University of Ljubljana who led the project, says that he first got the idea for the device while at a conference in San Francisco, listening to a talk by Stefan W. Hell about stimulated emission depletion (STED) microscopy. The imaging technique, for which Hell won a Nobel Prize in Chemistry in 2014, uses two lasers to produce an extremely small light beam to scan objects. “When I saw this, I said, This is manipulation light by light, right?” Muševič recalls.

His realization inspired a device into which a laser pulse is fired. Whether or not this beam makes it out of the device depends on whether or not a second pulse is fired less than a nanosecond afterwards.

A liquid crystal photonic switch

The device consists of a spherically shaped bead of liquid crystal, held in shape by its elastic material properties and the forces between its molecules, infused with a fluorescent dye and trapped between four upright cone-shaped polymer structures that guide light in and out of the device. When a laser pulse is sent through one of the four polymer waveguides, the light is quickly transferred into the liquid crystal, exciting the fluorescent dye. In a process known as whispering gallery mode resonance, the photons inside the liquid crystal are reflected back inside each time they hit the liquid’s spherical surface. The result is that light circulates inside the cavity until it is eventually reflected into one of the waveguides, which then emits the photons out in a laser beam.

The team realized that sending a second laser pulse of a different color into the waveguides before the liquid crystal started emitting light from the first laser pulse resulted in stimulated emission of the excited dye molecules. The photons from the second laser pulse, which had to be fired into the waveguides after the first laser pulse, interact with the already-excited dye molecules. The interaction causes the dye to emit photons identical to those in the second pulse while depleting the energy from the first pulse. The second laser beam, called the STED beam, is amplified by the process, while the light from the first pulse is so diminished that it isn’t emitted at all. Because the outcome of the first laser pulse could be controlled using the second laser pulse, the team had successfully demonstrated the control of light by light.

Vandna Sharma, Jaka Zaplotnik, et al.

According to the Ljubljana team, the energy efficiency of the liquid crystal approach is much better than previous soft-matter techniques, which had typically involved using intense light fields to change material properties of the soft matter, such as the index of refraction. The new method reduces the energy needed by more than a factor of a hundred. Because the STED laser pulse circulates repeatedly in the crystal, a single photon can deplete many dye molecules of the energy from the first laser pulse.

Miha Ravnik, a theoretical physicist also at the University of Ljubljana who worked on the project, explains that control of light by light is essential in soft-matter photonic logic gates. “You can very much control when [light] is generated and in which direction,” Ravnik says of the light shined into the polymer waveguides. “And this gives you, then, this capability that you create logical operations with light.”

Aside from its potential in photonic logical circuits, the team’s approach presents several technical advantages over photonics made from silicon or other hard materials, Muševič says. For example, using soft matter greatly simplifies the manufacturing process. The liquid crystal in the team’s device can be inserted in less than a second, but manufacturing a similar structure with hard materials is difficult. Additionally, soft-matter devices can be manufactured at much lower temperatures than silicon and other hard materials. Muševič also points out that soft matter presents an opportunity to experiment with the geometry of the device. With liquid crystals “you can make many different kinds of cavities,” says Muševič. “You have, I would say, a lot of engineering space.”

Ravnik is excited for the potential of the team’s breakthrough, particularly as a step toward photonic computing and even photonic neural networks. But, he recognizes that these developments are far down the line. “There’s no way this technology can compete with current neural network implementation at all,” he admits. Still, the possibilities are tantalizing. “The energy losses are predicted to be extremely low, the speeds for calculation extremely high.”

Unlike Superman, researchers at Adelaide University in Australia don’t claim to possess X-ray vision, but they have found a way to remotely observe the electrical activity of transistors inside a chip while they are working and without disturbing their operation. Rather than X-rays, the scientists use terahertz waves to detect tiny changes associated with the motion of electric charge inside packaged semiconductors.

Though still in the early stages of development, if refined and scaled up, this noninvasive probing system could change the way chips are tested, reducing reliance on techniques such as electronic probing and X-ray inspection, which can produce fine images of a chip’s structure but cannot observe its electrical behavior.

“We built the system with off-the-shelf components,” says Withawat Withayachumnankul, professor of engineering at Adelaide University and group leader for the research, which also involved colleagues at Virginia Diodes, in the United States, and at the Hasso Plattner Institute and the University of Potsdam, in Germany. “It requires line-of-sight, but it can penetrate chip-packaging materials that are nonmetallic.”

RELATED: X-ray Upgrade Can See Transistors in 3D

The operation begins with a vector network analyzer (VNA)—a laboratory tool that can generate a microwave signal with a known frequency and phase. The signal is converted into a terahertz wave by a device called a VNA frequency extender (supplied by Virginia Diodes), which then radiates the wave toward the chip to be tested. Before reaching the target, the terahertz radiation passes through an objective serving as a focusing lens, which concentrates the beam onto an area as small as 1 square millimeter—big enough to contain 5 bipolar junction transistors in this experiment.

When transistors switch on and off, they slightly alter the signal’s properties, and the reflected wave is returned along the same path to a receiver in the VNA extender. There, it is down-converted back to the microwave frequency and compared with the original signal.

By measuring the tiny differences in amplitude and phase, the system can infer changes in the movement of charge inside the chip. In particular, the researchers found that as the PN junctions in monitored transistors became more conductive—with more charge carriers present—the reflected terahertz signal became stronger.

“I’m not aware of any inspection technology that can do this. That’s exciting”—Daniel Mittleman, Brown University

A device called a homodyne quadrature receiver plays a central role in the process. It compares a signal with a matched-frequency reference to detect changes. Normally employed at lower frequencies, it is used here to detect extremely small, fast changes in the terahertz signal that would otherwise be invisible.

“We had to hack it to work in the terahertz domain, given the complexity of measuring both the strength and timing of a wave at such high frequencies,” says Withayachumnankul.

Because the terahertz wavelength is much larger than the feature being probed, the interaction produces only a very small change in the reflected signal. Noise from the oscillator in the VNA that produces the original microwave signal can easily obscure that change. “That’s why we opted to use a homodyne quadrature receiver to compare the probe signal with the original,” says Withayachumnankul. “Noise that is shared by both signals is largely canceled in the comparison, leaving only the changes induced by the chip’s electrical activity to stand out.”

“Homodyne detection is critical here,” says Daniel Mittleman, professor of engineering at Brown University, in Rhode Island. “It is what allows one to detect the changes in the terahertz signal imposed by the much lower-frequency megahertz electrical modulation of the [transistors being monitored]. Typical terahertz detection schemes would not be able to see that.”

Terahertz radiation from a horn antenna [center] reflects off of a diode [right].Bryce Chung, Harrison Lees, et al.

Reflected terahertz radiation

Besides being able to penetrate nonmetallic semiconductor packaging, terahertz waves are a harmless and nonionizing form of electromagnetic radiation, and so have the potential to provide a safer alternative to inspection methods that rely on X-ray or invasive probing, according to the researchers.

“The plastic and ceramic used in most semiconductor packaging are thin enough that they do not excessively absorb terahertz waves,” says Withayachumnankul. “So there is no need to remove it. This means we can measure semiconductor activity in situ.”

While packaging may not be a problem for terahertz inspection, other aspects of modern chips might be. “In general, modern chips consist of many layers, sometimes just interconnects, and sometimes also active circuity,” says Mittleman. “It’s not clear that these layers are all transparent to terahertz radiation.” Consequently, he points out that this detection technique may have a problem if the target device is buried under a dozen other layers. “If those overlayers are opaque, then this technique cannot be used to diagnose that deeply buried device. That’s the limitation of the idea.”

Given the relatively low sensitivity of the system at this stage of development, the researchers have mostly confined their testing to discrete devices, monitoring in real time the changes in switching and states of devices such as rectifier diodes, bipolar junction transistors, and field-effect transistors (FETs). More recently, they have moved on to test integrated circuits containing up to half a dozen FETs.

The next major challenge is to improve the technique’s sensitivity in order to examine more densely integrated chips. “We have several ideas how to do this, but I’m not ready to talk about them yet,” says Withayachumnankul.

Eventually, after the technology is refined and perfected, he says this approach would be particularly attractive for safety-critical applications such as high-power electronics, where devices cannot easily be taken offline without causing operational disruption. Additionally, with the help of his collaborators in Germany, Withayachumnankul is aiming to use the technique to read encrypted data in chips, which could have implications for security.

“The idea of using terahertz imaging for studying semiconductor devices has been around for quite a while,” says Mittleman. But this work opens the possibility of “diagnosis of a device under operation within a package. I’m not aware of any inspection technology that can do this. That’s exciting.”

The research was published in IEEE Journal of Microwaves on 17 March 2026.

By many estimates, quantum computers will need millions of qubits to realize their potential applications in cybersecurity, drug development, and other industries. The problem is, anyone who has wanted to simultaneously control millions of a certain kind of qubit has run into the problem of trying to control millions of laser beams.

That’s exactly the challenge that was faced by scientists working on the MITRE Quantum Moonshot project, which brought together scientists from MITRE, MIT, the University of Colorado at Boulder, and Sandia National Laboratories. The solution they developed came in the form of an image projection technology that they realized could also be the fix for a host of other challenges in augmented reality, biomedical imaging, and elsewhere. The device is a 1-square-millimeter photonic chip capable of projecting the Mona Lisa onto an area smaller than the size of two human egg cells.

“When we started, we certainly never would have anticipated that we would be making a technology that might revolutionize imaging,” says Matt Eichenfield, one of the leaders of the Quantum Moonshot project, a collaborative research effort focused on developing a scalable, diamond-based quantum computer, and a professor of quantum engineering at the University of Colorado at Boulder. Each second, their chip is capable of projecting 68.6 million individual spots of light—called scannable pixels—to differentiate them from physical pixels. That’s more than 50 times the capability of previous technology, such as micro-electromechanical systems (MEMS) micromirror arrays.

“We have now made a scannable pixel that is at the absolute limit of what diffraction allows,” says Henry Wen, a visiting researcher at MIT and a photonics engineer at QuEra Computing.

The chip’s distinguishing feature is an array of tiny microscale cantilevers, which curve away from the plane of the chip in response to voltage and act as miniature “ski jumps” for light. Light is channeled along the length of each cantilever via a waveguide and exits at its tip. The cantilevers contain a thin layer of aluminum nitride, a piezoelectric that expands or contracts under voltage, thus moving the micromachine up and down and enabling the array to scan beams of light over a two-dimensional area.

Despite the magnitude of the team’s achievement, Eichenfield says that the process of engineering the cantilevers was “pretty smooth.” Each cantilever is composed of a stack of several submicrometer layers of material and curls approximately 90 degrees out of the plane at rest. To achieve such a high curvature, the team took advantage of differences in the contraction and expansion of individual layers caused by physical stresses in the material resulting from the fabrication process. The materials are first deposited flat onto the chip. Then, a layer in the chip below the cantilever is removed, allowing the material stresses to take effect, releasing the cantilever from the chip and allowing it to curl out. The top layer of each cantilever also features a series of silicon dioxide bars running perpendicular to the waveguide, which keep the cantilever from curling along its width while also improving its lengthwise curvature.

A micro-cantilever wiggles and waggles to project light in the right place.Matt Saha, Y. Henry Wen, et al.

What was more of a challenge than engineering the chip itself was figuring out the details of actually making the chip project images and videos. Working out the process of synchronizing and timing the cantilevers’ motion and light beams to generate the right colors at the right time was a substantial effort, according to Andy Greenspon, a researcher at MITRE who also worked on the project. Now, the team has successfully projected a variety of videos from a single cantilever, including clips from the movie A Charlie Brown Christmas.

The chip projected a roughly 125-micrometer image of the Mona Lisa.Matt Saha, Y. Henry Wen, et al.

Because the chip can project so many more spots in any given time interval than any previous beam scanners, it could also be used to control many more qubits in quantum computers. The Quantum Moonshot program’s mission is to build a quantum computer that can be scaled to millions of qubits. So clearly, it needs a scalable way of controlling each one, explains Wen. Instead of using one laser per qubit, the team realized that not every qubit needed to be controlled at every given moment. The chip’s ability to move light beams over a two-dimensional area would allow them to control all of the qubits with many fewer lasers.

Another process that Wen thinks the chip could improve is scanning objects for 3D printing. Today, that typically involves using a single laser to scan over the entire surface of an object. The new chip, however, could potentially employ thousands of laser beams. “I think now you can take a process that would have taken hours and maybe bring it down to minutes,” says Wen.

Wen is also excited to explore the potential of different cantilever shapes. By changing the orientations of the bars perpendicular to the waveguide, the team has been able to make the cantilevers curl into helixes. Wen says that such unusual shapes could be useful in making a lab-on-a-chip for cell biology or drug development. “A lot of this stuff is imaging, scanning a laser across something, either to image it or to stimulate some response. And so we could have one of these ski jumps curl not just up, but actually curl back around, and then move around and scan over a sample,” Wen explains. “If you can imagine a structure that will be useful for you, we should try it.”

Researchers have made a Wi-Fi receiver that’s tough enough to work inside a nuclear reactor. They hope the receiver might be part of a wireless communications system for robotics used to decommission reactors.

Yasuto Narukiyo, a graduate student at the Institute of Science Tokyo, presented the wireless receiver at the IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco in February. The receiver endured a total radiation dose of 500 kilograys, orders of magnitude higher than the doses typically tolerated by electronics in outer space.

After the 2011 nuclear disaster at the Fukushima Daiichi plant, engineers began using robots to help characterize and clean up the site. Most of these require local area network (LAN) cables that can get tangled, says Narukiyo. His team, which includes his advisor Atsushi Shirane and Masaya Miyahara of Japan’s High Energy Accelerator Research Organization (KEK), is aiming to develop a wireless system for controlling robots in this harsh environment.

Even under less dramatic circumstances, nuclear plants don’t last forever, and they need to be safely dismantled and decontaminated so the sites can be reused, a process called decommissioning. The process is lengthy, and risks exposing people to radiation, which is why engineers hope robots can come to the rescue.

The need for such robots is only growing. According to a 2024 study, of 204 reactors that have been closed, only 11 plants with a capacity over 100 megawatts have been fully decommissioned, and 200 more reactors will reach the end of their lifetimes in the next 20 years.

While electronics for space exploration are typically required to endure radiation doses of 100 to 300 grays over three years, a robot operating in a nuclear reactor needs to endure more than 500 kGy over the course of six months, says Narukiyo—at least 1,000 times the dosage. A robotic arm made by KUKA was able to withstand just 164.55 Gy of damage before failing. For comparison, the lens of the eye absorbs just 60 milligrays during a CT scan of the brain.

Radiation Hardening

To “harden” the 2.4-gigahertz Wi-Fi receiver against intense levels of radiation, Narukiyo and his team changed its mix of components, minimized the total number of transistors, and tinkered with the geometry of the transistors that were left.

The transistors, silicon MOSFETs (metal-oxide semiconductor field-effect transistors), contain an oxide layer that’s particularly vulnerable to radiation damage. Blasts of gamma rays can trap positive charges in the oxide, degrading the device’s performance and causing errors. So using fewer of them minimizes the problem. The researchers also made each transistor’s gate longer and wider. The gate controls the flow of current—longer, wider gates perform better under exposure to radiation.

Researchers tested the Wi-Fi receiver by placing it on top of a radiation source.Yasuto Narukiyo, Sena Kato, et al.

The group also considered the differences in how radiation affects PMOS transistors, MOSFETs in which current is carried primarily by positive charges, and NMOS, in which it is carried by electrons. PMOS transistors are more vulnerable to radiation damage because positive charge gets trapped in both the oxide and at the interface between the oxide and the rest of the semiconductor. These add up and shift the transistor towards the “off” state, says Narukiyo. To compensate, the new receiver design minimizes the use of PMOS, replacing these transistors with other elements such as inductors that don’t have an oxide layer. NMOS transistors are more resilient, says Narukiyo, because positive charges trapped in the oxide are to some extent canceled out by negative charges that get trapped at the interface.

Narukiyo and his team measured the performance of the receiver before exposure to radiation, and again after blasting it with a total dose of 300 kGy and then 500 kGy. Before being irradiated, it showed comparable performance to typical Wi-Fi receivers. After reaching the highest radiation dose, the gain of the receiver had decreased by about 1.5 decibel.

Narukiyo says the receiver is hardened enough, and now he hopes to improve its performance. He’s also working on a transmitter, which would allow for two-way communications. This is more challenging due to the need to produce high levels of current to generate the Wi-Fi signal. He says an earlier version he tried was broken by a 300 kGy dose. The group is exploring using other semiconductors, such as diamond, to toughen the transmitter.

This article appears in the June 2026 print issue as “Wi-Fi Receiver Can Survive Inside a Nuclear Reactor.”

Jupiter’s orbit is one of the harshest places in the solar system when it comes to radiation exposure. The planet has a potent magnetic field that extends out past its huge system of moons, and that field breaks down and ionizes sulfur dioxide gas spewed by the volcanic moon Io, feeding a giant radiation belt of fast-moving charged particles. It’s a challenging environment in which to operate a camera, to say the least.

A self-healing CMOS imager could help extend the lifetime of cameras sent into such high-radiation areas. The imager, presented last month at the IEEE International Solid State Circuits Conference (ISSCC) in San Francisco, also performs aggressive compression to minimize the amount of data a spacecraft has to transmit from faraway locales like Io. The imager could also be used in satellites in Earth’s orbit, which catch damage from cosmic rays, too.

Engineers controlling Interplanetary craft have already healed radiation-damaged circuits using heat. In December 2023, NASA used the method to repair JunoCam, a visible-light camera in orbit around Jupiter. By its 56th orbit, all of Juno’s images taken with the tool were corrupted by radiation damage. The NASA team tried heating the entire camera to see if it would help—and it worked. As the spacecraft approached Io again, images began streaming in.

The new self-healing imager system is designed to fix these kinds of problems as they arise, one pixel at a time.

At the heart of the prototype imager is a 128-by-128-pixel array. As in other CMOS imagers, each pixel is made up of a photodiode and several transistors to amplify and control the photodetector’s signal. Other circuits on the chip detect regions of interest in the images by searching for edges, performing image compression, and reading out the pixels by row and column.

Not all of the data in an image is important, says Quan Cheng, who worked on the prototype imager at the Southern University of Science and Technology, in Shenzen, and at Kyoto University. Cheng, who is now at Brown University, presented the circuit design at ISSCC. “We just capture the region of interest.” That cuts down on the imager’s data output by about 75 percent.

Fixing Radiation Damage to Electronics

Radiation harms circuits in multiple ways, says Cheng. Bombardment by high-speed protons, electrons, and gamma rays can trap charges in the semiconductor and degrade the oxide layer used for insulation in CMOS devices. Radiation can also knock atoms out of their places in the semiconductor crystal. All that adds up to damaged pixels, current flowing when no photons are being detected in the pixel array—called “dark current”—and higher current leakage in other parts of the chip. Adding a bit of heat—slowly through a process called annealing—can fix much of this damage. The annealing heat provides enough energy to allow trapped charges to escape and move atoms back into place to repair the crystalline structure of the silicon.

The imager detects damaged or “hot” pixels by periodically performing a readout while the camera is shuttered and sensing whether any pixels exceed a defined current threshold. To heal a damaged pixel, the system heats it by applying a strong current. Imaging can still be performed by other parts of the array while a pixel is healing. During the healing process, readouts from the affected column of pixels are “masked” by a control circuit. The line that’s blacked out of such an image is filled in by averaging the readouts from pixels in the columns adjacent to it. Damage to digital logic in the imager can also be healed. The chip is designed to detect logic errors and similarly heats up transistors by applying a strong voltage pulse.

The team tested the chip by bombarding it with a radiation dose that’s equivalent to what the imager would experience during 30 days near Jupiter, about 20 kilograys. Radiation exposure increased dark current in the device by about 181 times, making an image unrecognizable. Four rounds of healing led to nearly full recovery of the image, and almost entirely eliminated current leakage in the logic section caused by radiation damage as well.

The design is not intended to replace other radiation hardening approaches such as adding shielding, but as an add-on, says Longyang Lin, a microelectronics researcher at Southern University of Science and Technology in Shenzhen who worked with Cheng. “It’s intended to further extend the lifetime” of imagers, he says.

“Their method requires far less space than competitive approaches by taking advantage of the addressability of the pixel array and pulsing power into the target circuit,” says Matt Francis, CEO of Ozark Integrated Circuits, in Arkansas, which specializes in circuits for extreme environments. Hardening semiconductors can entail enclosing sensors or using different materials with wider bandgaps. These designs tend to take up more real estate on a chip, or increase costs, says Francis.

An in-depth examination of how rising power density, 3D integration, and novel materials are outpacing legacy thermal measurement — and what advanced metrology must deliver.

What Attendees will Learn

1. Why heat is now the dominant constraint on semiconductor scaling — Explore how heterogeneous integration, 3D stacking, and AI-driven power density have shifted the primary bottleneck from lithography to thermal management, with heat flux projections exceeding 1,000 W/cm² for next-generation accelerators.
   
2. How extreme material properties are redefining thermal design requirements —Understand the measurement challenges posed by nanoscale thin films where bulk assumptions fail, engineered ultra-high-conductivity materials (diamond, BAs, BNNTs), and devices operating above 200 °C in wide-band gap systems.
3. Why interfaces and buried layers now govern reliability — Examine how thermal boundary resistance at bonded interfaces, TIM layers, and dielectric stacks has become a first-order reliability accelerator.
4. What a thermal-first design workflow looks like in practice — Learn how measured, scale-appropriate thermal properties can be integrated early in the design cycle to calibrate models, reduce uncertainty, and prevent costly late-stage failures across advanced packaging and 3D architectures.

Light-warping physics made “invisibility cloaks” a possibility. Now two startups hope to harness the science underlying this advance to boost the bandwidth of data centers and speed artificial intelligence.

Roughly 20 years ago, scientists developed the first structures capable of curving light around objects to conceal them. These are composed of optical metamaterials—materials with structures smaller than the wavelengths they are designed to manipulate, letting them bend light in unexpected ways.

The problem with optical cloaks? “There’s no market for them,” says Patrick Bowen, cofounder and CEO of photonic computing startup Neurophos in Austin, Texas. For instance, each optical cloak typically works only on a single color of light instead of on all visible colors as you might want for stealth applications.

Now companies are devising more practical uses for the science behind cloaks, such as improving the switches that connect computers in data centers for AI and other cloud services. Increasingly, data centers are looking to use optical circuit switches to overcome the bandwidth limits and power consumption of conventional electronic switches and networks that require converting data between light to electrons multiple times.

RELATED: Semiconductor Industry Closes in on 400 Gb/s Photonics Milestone

However, today’s optical switching technologies have drawbacks of their own. For instance, ones that depend on silicon photonics face problems with energy efficiency, while those that rely on microelectromechanical systems (MEMS) can prove unreliable, says Sam Heidari, CEO of optical metasurface startup Lumotive in Redmond, Wash.

Instead, Lumotive has developed metamaterials with adjustable properties. Its new microchip, which debuted 19 March, is covered with copper structures built using standard chipmaking techniques. Between these copper features are liquid crystal elements. The structure of these elements are electronically programmable, just like in liquid crystal displays (LCDs), to alter the optical properties of the metamaterial chip.

The microchip can precisely steer, lens, shape, and split beams of light reflected off its surface. It can perform all the same functions as multiple optical components with no moving parts in a programmable way in real time, according to Lumotive. “Having no moving parts significantly improves reliability,” Heidari says.

“We had to go through a lot of R&D at the foundries to not only make our devices functional, but also commercially viable in terms of the right cost and right reliability,” Heidari says.

The company says its new chips are capable of manipulating not only the industry’s standard of 256 by 256 ports, but could scale up to 10,000 by 10,000. “We think this is game-changing for data centers,” Heidari says. Lumotive plans to launch its first optical switches at the end of 2026.

Optical Computing With Metamaterials

Similarly, Neurophos hopes its technology may be transformative for artificial intelligence. Since AI is proving energy hungry when run on conventional electronics, scientists are exploring optical computing as a low-power alternative by processing data with light instead of electrons.

However, optical processors in the works today are typically far too bulky to achieve a compute density competitive with the best modern electronic processors, Bowen says. Neurophos says it can use metamaterials to build optical modulators—the optical equivalent of a transistor—that are 1/10,000th the size of today’s designs using standard chipmaking processes. “It’s entirely CMOS,” Bowen says. “There are no exotic materials in it.”

When a laser beam encoding data shines on a Neurophos chip, the way in which each metamaterial element is configured alters the reflected beam to encode results from complex AI tasks. “We basically fit a 1,000- by-1,000 array of optical modulators on a tiny 5-by-5-millimeter area on a chip,” Bowen says. “If you wanted to do that with off-the-shelf silicon photonics, your chip would be a square meter in size.”

All in all, Bowen claims the Neurophos microchip will offer 50 times greater compute density and 50 times greater energy efficiency than Nvidia’s Blackwell-generation GPU. The company says that hyperscalers—the world’s biggest cloud service providers—will evaluate two upcoming proof-of-concept chips this year. Neurophos is targeting its first systems for early 2028, with production ramping mid-2028.

Always-on vision systems might be used in autonomous vehicles, robotics, or to help consumer electronics save power by turning screens off when no one’s around. But to be used in such a way, these systems need to minimize their own power consumption.

An always-on computer vision system developed by Nvidia researchers can detect human faces in less than a millisecond. The face detector, which is part of a chip that could be integrated into robots, autonomous vehicles, or laptops, saves power by storing all data locally and “racing to sleep” after detections. Nvidia electrical engineer Ben Keller presented the system on 18 February at the IEEE International Solid State Circuits Conference in San Francisco.

Efficient Vision-Processing Technology

According to the researchers, this kind of vision processing typically requires about 10 watts. But that’s too much power to leave a face-detection system on continuously. The Nvidia system on chip (SoC) uses less than 5 milliwatts with a frame rate of 60 frames per second.

The system refreshes to process a new image every 16.7 milliseconds, and is fully powered on only for 5 percent of that time, says Keller. Within 787 microseconds, the SoC calls on a deep-learning accelerator to determine whether or not a human face is present, with about 99 percent accuracy.

The Nvidia team carefully designed the system to perform the detection rapidly and save power. Most parts of the SoC are powered off by default. A subsystem that uses less than 10 mW remains on. This subsystem is dubbed Always-on Low-Power Accelerator, or Alpha-Vision. It consists of a deep learning accelerator, a small CPU, and a subsystem to do certain computations physically near where data is stored.

Alpha-Vision uses a deep neural network to recognize faces, which requires a lot of data—in other words, a potential power drain. To save power and speed up detections, all the necessary data is stored locally in a relatively large area of SRAM adding up to 2 megabytes. To prevent SRAM leakage from dominating power usage, the face-recognition system rushes through its work and then quickly puts the SRAM into a low-power sleep mode. The researchers call this approach “race to sleep.”

The Nvidia team proposed several possible uses of such a system. A laptop computer integrating the face sensor could save energy by turning its display off when the user walks away, and then turning it back on when they return. The goal would be to provide a seamless experience—no need to type in a password. Keller says systems based on these designs might also be used to provide always-on vision for autonomous vehicles, drones, and robotics.

This post was corrected on 18 March to more accurately describe the state of the SRAM.

This week, over 30,000 people are descending upon San Jose, Calif., to attendNvidia GTC, the so-called Superbowl of AI—a nickname that may or may not have been coined by Nvidia. At the main event Jensen Huang, Nvidia CEO, took the stage to announce (among other things) a new line ofnext-generation Vera Rubin chips that represent a first for the GPU giant: a chip designed specifically to handle AI inference. The Nvidia Groq 3 language processing unit (LPU) incorporates intellectual property Nvidialicensed from the startup Groq last Christmas Eve for US $20 billion.

“Finally, AI is able to do productive work, and therefore the inflection point of inference has arrived,” Huang told the crowd. “AI now has to think. In order to think, it has to inference. AI now has to do; in order to do, it has to inference.”

Training and inference tasks have distinct computational requirements. While training can be done on huge amounts of data at the same time and can take weeks, inference must be run on a user’s query when it comes in. Unlike training, inference doesn’t require running costlybackpropagation. With inference, the most important thing is low latency—users expect the chatbot to answer quickly, and for thinking or reasoning models, inference runs many times before the user even sees an output.

Over the past few years, inference-specific chip startups were experiencing a sort of Cambrian explosion, with different companies exploring distinct approaches to speed up the task. The startups includeD-matrix, with digital in-memory compute;Etched, with an ASIC for transformer inference;RainAI, with neuromorphic chips;EnCharge, with analog in-memory compute;Tensordyne, with logarithmic math to make AI computations more efficient;FuriosaAI, with hardware optimized for tensor operation rather than vector-matrix multiplication, and others.

Late last year, it looked like Nvidia had picked one of the winners among the crop of inference chips when it announced its deal with Groq. The Nvidia Groq 3 LPU reveal came a mere two and a half months after, highlighting the urgency of the growing inference market.

Memory bandwidth and data flow

Groq’s approach to accelerating inference relies on interleaving processing units with memory units on the chip. Instead of relying on high-bandwidth memory (HBM) situated next to GPUs, it leans on SRAM memory integrated within the processor itself. This design greatly simplifies the flow of data through the chip, allowing it to proceed in a streamlined, linear fashion.

“The data actually flows directly through the SRAM,”Mark Heaps said at the Supercomputing conference in 2024. Heaps was a chief technology evangelist at Groq at the time and is now director of developer marketing at Nvidia. “When you look at a multicore GPU, a lot of the instruction commands need to be sent off the chip, to get into memory and then come back in. We don’t have that. It all passes through in a linear order.”

Using SRAM allows that linear data flow to happen exceptionally fast, leading to the low latency required for inference applications. “The LPU is optimized strictly for that extreme low latency token generation,” saysIan Buck, VP and general manager of hyperscale and high-performance computing at Nvidia.

Comparing the Rubin GPU and Groq 3 LPU side by side highlights the difference. The Rubin GPU has access to a whopping 288 gigabytes of HBM and is capable of 50 quadrillion floating-point operations per second (petaFLOPS) of 4-bit computation. The Groq 3 LPU contains a mere 500 megabytes of SRAM memory and is capable of 1.2 petaFLOPS of 8-bit computation. On the other hand, while the Rubin GPU has a memory bandwidth of 22 terabytes per second, at 150 TB/s the Groq 3 LPU is seven times as fast. The lean, speed-focused design is what allows the LPU to excel at inference.

The new inference chip underscores the ongoing trend of AI adoption, which shifts the computational load from just building ever bigger models to actually using those models at scale. “Nvidia’s announcement validates the importance of SRAM-based architectures for large-scale inference, and no one has pushed SRAM density further than d-Matrix,” says d-Matrix CEO Sid Sheth. He’s betting that data center customers will want a variety of processors for inference. “The winning systems will combine different types of silicon and fit easily into existing data centers alongside GPUs.”

Inference-only chips may not be the only solution. Late last week, Amazon Web Services said that it will deploy a new kind of inferencing system in its data centers. The system is a combination of AWS’s Tranium AI accelerator and Cerebras Systems’ third generation computer CS-3, which is built around the largest single chip ever made. The two-part system is meant to take advantage of a technique called inference disaggregation. It separates inference into two parts—processing the prompt, called prefill, and generating the output, called decode. Prefill is inherently parallel, computationally intensive, and doesn’t need much memory bandwidth, while decode is a more serial process that needs a lot of memory bandwidth. Cerebras has maximized the memory bandwidth issue by building 44 GB of SRAM on its chip connected by a 21 PB/s network.

Nvidia, too, intends to take advantage of inference disaggregation in its new compute rack, called the Nvidia Groq 3 LPX. Each tray within the rack will house 8 Groq 3 LPUs. The LPX will split the inference task with a Vera Rubin NVL72, Nvidia’s existing GPU and CPU rack. The prefill and the more computationally intensive parts of the decode are done on Vera Rubin, while the final part is done on the Groq 3 LPU, leveraging the strengths of each chip. “We’re in volume production now,” Huang said.

Correction on 4/8/26: a previous version of this article incorrectly stated that the Nvidia Groq 3 LPX contains a Vera Rubin chip in each tray. In fact, each tray contains 8 Groq 3 LPUs and no Vera Rubins, but the whole rack is designed to work in concert with an NVL72 rack, which houses Vera Rubin chips.

This article appears in the May 2026 print issue as “The Era of AI Inference Is Almost Here.”

As the bandwidth and power demands of AI data centers necessitate a transition from electrical to optical scaleup networking, one component has been conspicuously absent from the co-packaged optics arsenal: the laser itself. That’s no longer the case. Last month, Tower Semiconductor and Scintil Photonics announced production of the world’s first single-chip DWDM light engine for AI infrastructure. DWDM, or dense wavelength division multiplexing, transmits multiple optical signals over a single fiber—greatly reducing power and latency while connecting dozens of GPUs.

Matt Crowley, the CEO of Scintil Photonics, says that the idea of multiplexing optically is not new. Indeed, it’s been around as long as the internet itself. In the 1990s, telecom companies buried huge amounts of optical fiber in the streets, assuming that one wavelength per fiber would eventually become the norm. When the telecom industry realized it’s possible to transport tens of wavelengths down a single fiber via multiplexing, it revolutionized the industry.

The reason that DWDM has not yet been deployed for data centers specializing in AI applications is that the technology is not yet scalable for cost and needs. “The data transmitted within an AI data center is the equivalent of massively scaling a supercomputer,” Crowley says. In particular, the challenge arises in scale-up networking, or directly connecting accelerators within a rack or cluster—as opposed to scale-out networking, which connects separate clusters within a data center. Optimizing dozens of GPUs and memory to function as a single entity demands seamless bandwidth and extremely low latency.

To increase bandwidth, reduce latency, and improve energy efficiency in AI data centers, network engineers have been replacing copper links with optical ones in the scale-out network. Now all eyes are on the scale-up network, pushing optical links closer to the processor itself, via optical components integrated within the same package as the processor—a concept called co-packaged optics, or CPO.

“Everything that a big chip company makes involves bonding an optical chip onto their GPU,” says Crowley. The CPO becomes an input/output chip for the processor. But without a scalable way to integrate lasers themselves into the same silicon process flow, it’s been impossible to feed multiple wavelengths per fiber onto one chip. Scintil and Tower will discuss their manufacturing road map and details at at the OFC 2026 Conference 17 to 19 March in Los Angeles.

Integrated Photonics for AI Networks

Scintil’s SHIP (Scintil Heterogeneous Integrated Photonics) technology integrates lasers, photodiodes, modulators, and other components onto a mass-produced silicon wafer. “It’s our version of CMOS,” says Crowley, but with a few tricks to get around the intrinsic challenges of binding an optical gain material to silicon.

The process starts with a standard 300-millimeter silicon photonics wafer, complete with passive optical components, from Tower Semiconductors. Next, the wafer is flipped upside down to expose its buried oxide layer. Bonding tiny squares of unpatterned InP/III-V semiconductor dies to that layer, precisely where they’re needed at each laser site, minimizes the amount needed of the expensive semiconductor material. Finally, photolithography tools etch diffraction gratings to form eight distributed feedback lasers.

“We’re not reinventing the laser,” says Crowley. Rather, the advanced photolithography tools translate into more precise spacing and wavelength stability than traditional manufacturing could provide on a silicon wafer.

The final product is the LEAF Light photonic integrated circuit, a chip that integrates two sets of eight distributed feedback arrays. Each fiber port delivers eight or 16 wavelengths with 100- or 200-gigahertz channel spacing, to ensure no overlap or mode hopping. A second ASIC chip hosts all the electronics to control and monitor the laser array.

Advancing CPO with Multiwavelength Lasers

“This is building the laser onto the CPO chip,” says Crowley. Nvidia and Broadcomm have already deployed CPO with a single wavelength per fiber, proving its workability in scale-out networking. “We’re enabling next-generation CPO for scale-up.”

Transmitting multiple wavelengths through a single fiber moves the industry toward a desirable “slow and wide” architecture. For example, instead of transmitting 400 gigabits per second over a single channel, or wavelength, the LEAF Light chip spreads 50 Gb/s over 8 channels, greatly increasing the data capacity per fiber and overall power efficiency. The design enables up to 1.6-terabit-per-second data speeds in a single fiber, and a recent Nvidia road map suggested that future DWDM interconnects could eventually enable sub-picojoule-per-bit operations.

Perhaps the most important benefit, according to Crowley, is in latency. “I need to maintain low latency between GPUs,” he says. If any individual processor operates faster than the network overall, the GPUs are always waiting for data bits to process—a problem that’s amplified in scale-up networks with tens or hundreds of GPUs. Forward-processing and error-correction on high-bandwidth channels increases the odds of poor latency. “The utilization rate of the GPUs just tanks,” says Crowley. Using low-bandwidth DWDM to connect multiple GPUs can double utilization.

Scintil and Tower will provide tens of thousands of units to customers by the end of 2026, and plan to increase production by an order of magnitude next year. By 2028, when customers intend to deploy DWDM in scale-up networks, the supply chain will be ready for them. “We’re excited about the possibilities it could open up,” says Crowley.

Living cells and tissues grown in the lab are vital tools for helping scientists learn about basic biology and test new drugs. Growing miniature organs on a chip from a person’s stem cells could even one day help doctors test personalized treatments.

Now, researchers have developed a lab-on-a-chip that adds a new feature to these systems: low-power grippers that can hold cells or tiny organ models called organoids in place. The CMOS-compatible lab-on-a-chip features shape-memory grippers and chemical sensors for detecting molecules such as neurotransmitters. The microcage array was presented in San Francisco on 18 February at the IEEE International Solid State Circuits Conference.

Researchers working on this multifunctional system hope it will be used to sense and manipulate biological samples of different sizes and potentially help direct the development of stem cells into organoids, which are used to study basic biology and drugs. Growing neural organoids in lab-on-a-chip systems, for instance, can help biologists study brain development and how it’s impacted by chemicals or drugs. Cage-like grippers could be used to hold samples in place, or to bring tissue samples next to each other to encourage their development.

Building bioelectronic systems directly on a chip is attractive because it makes it easy to integrate many different features, including chemical sensing, electrical sensing and stimulation, and physical manipulation. However, manipulating biological samples on CMOS chips can be tricky, says Adam Wang, an electrical engineer at ETH Zurich. Optical and acoustic tweezers, for example, can heat up, while the electric fields used to generate motion in dieletrophoresis can be weakened by high concentrations of ions in the media used to support cells and tissues. These methods also require continuous power inputs. Wang presented the research on behalf of lead student Zhikai Huang, who was unable to attend.

How the Microcages Work

The ETH chip integrates tiny grippers to “cage” biological samples. These grippers are based on so-called shape-memory alloys, layered metal structures that change their shape in response to electric signals, then hold that shape without the need for any additional power.

The ETH chip holds an array of nine sets of microcages, along with control electrodes and electrodes for chemical sensing. At each spot on the array, cages of three different sizes are nested together like rows of concentric flower petals. Their arms are 100, 150, and 280 micrometers long. The smallest might be used to grab single cells while the largest is designed to grapple with whole organoids.

The arms are made of layered platinum and titanium. Each of the three different-sized sets has its own dedicated control electrode. In response to the polarity and magnitude of a signal, the cage arms will either bend and curl upward or flatten back down onto the surface. The electric signal triggers the movement by changing the electrochemical state of the platinum. Once the cages change shape, they stay in place with no additional power, unless they receive an electrical order to open or close again. The array includes electrochemical sensors in the form of electrodes made of gold, platinum, and palladium. Using different electrode materials with different properties enhances the sensitivity of the system, says Wang. And all these materials can operate in electrolytes, including the cell culture media that help sustain biological cells and tissues in the lab.

At the conference, Wang presented the circuit design, and initial tests using the cages to grip onto glass beads and measure concentrations of ferrocyanide, a chemical commonly used to test lab-on-a-chip sensors. Next, they hope to demonstrate that the array can delicately handle biological cells and organoids, and measure biochemicals such as neurotransmitters. Wang says future versions of the CMOS platform could integrate more electrodes for electrical sensing and stimulation of nerve cells.

Worried that your latest ask to a cloud-based AI reveals a bit too much about you? Want to know your genetic risk of disease without revealing it to the services that compute the answer?

There is a way to do computing on encrypted data without ever having it decrypted. It’s called fully homomorphic encryption, or FHE. But there’s a rather large catch. It can take thousands—even tens of thousands—of times as long to compute on today’s CPUs and GPUs than simply working with the decrypted data.

So universities, startups, and at least one processor giant have been working on specialized chips that could close that gap. Last month at the IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco, Intel demonstrated its answer, Heracles, which sped up FHE computing tasks as much as 5,000-fold compared to a top-of the-line Intel server CPU.

Startups are racing to beat Intel and each other to commercialization. But Sanu Mathew, who leads security circuits research at Intel, believes the CPU giant has a big lead, because its chip can do more computing than any other FHE accelerator yet built. “Heracles is the first hardware that works at scale,” he says.

The scale is measurable both physically and in compute performance. While other FHE research chips have been in the range of 10 square millimeters or less, Heracles is about 20 times that size and is built using Intel’s most advanced, 3-nanometer FinFET technology. And it’s flanked inside a liquid-cooled package by two 24-gigabyte high-bandwidth memory chips—a configuration usually seen only in GPUs for training AI.

RELATED: How to Compute with Data You Can’t See

In terms of scaling compute performance, Heracles showed muscle in live demonstrations at ISSCC. At its heart the demo was a simple private query to a secure server. It simulated a request by a voter to make sure that her ballot had been registered correctly. The state, in this case, has an encrypted database of voters and their votes. To maintain her privacy, the voter would not want to have her ballot information decrypted at any point; so using FHE, she encrypts her ID and vote and sends it to the government database. There, without decrypting it, the system determines if it is a match and returns an encrypted answer, which she then decrypts on her side.

On an Intel Xeon server CPU, the process took 15 milliseconds. Heracles did it in 14 microseconds. While that difference isn’t something a single human would notice, verifying 100 million voter ballots adds up to more than 17 days of CPU work versus a mere 23 minutes on Heracles.

Looking back on the five-year journey to bring the Heracles chip to life, Ro Cammarota, who led the project at Intel until last December and is now at University of California, Irvine, says “We have proven and delivered everything that we promised.”

FHE Data Expansion

FHE is fundamentally a mathematical transformation, sort of like the Fourier transform. It encrypts data using a quantum-computer-proof algorithm, but, crucially, uses corollaries to the mathematical operations usually used on unencrypted data. These corollaries achieve the same ends on the encrypted data.

One of the main things holding such secure computing back is the explosion in the size of the data once it’s encrypted for FHE, Anupam Golder, a research scientist at Intel’s circuits research lab, told engineers at ISSCC. “Usually, the size of cipher text is the same as the size of plain text, but for FHE it’s orders of magnitude larger,” he said.

While the sheer volume is a big problem, the kinds of computing you need to do with that data is also an issue. FHE is all about very large numbers that must be computed with precision. While a CPU can do that, it’s very slow going—integer addition and multiplication take about 10,000 more clock cycles in FHE. Worse still, CPUs aren’t built to do such computing in parallel. Although GPUs excel at parallel operations, precision is not their strong suit. (In fact, from generation to generation, GPU designers have devoted more and more of the chip’s resources to computing less-and-less-precise numbers.)

FHE also requires some oddball operations with names like “twiddling” and “automorphism,” and it relies on a compute-intensive noise-cancelling process called bootstrapping. None of these things are efficient on a general-purpose processor. So, while clever algorithms and libraries of software cheats have been developed over the years, the need for a hardware accelerator remains if FHE is going to tackle large-scale problems, says Cammarota.

The Labors of Heracles

Heracles was initiated under a Defense Advanced Research Projects Agency (DARPA) program five years ago to accelerate FHE using purpose-built hardware. It was developed as “a whole system-level effort that went all the way from theory and algorithms down to the circuit design,” says Cammarota.

Among the first problems was how to compute with numbers that were larger than even the 64-bit words that are today a CPU’s most precise. There are ways to break up these gigantic numbers into chunks of bits that can be calculated independently of each other, providing a degree of parallelism. Early on, the Intel team made a big bet that they would be able to make this work in smaller, 32-bit chunks, yet still maintain the needed precision. This decision gave the Heracles architecture some speed and parallelism, because the 32-bit arithmetic circuits are considerably smaller than 64-bit ones, explains Cammarota.

At Heracles’s heart are 64 compute cores—called tile-pairs—arranged in an eight-by-eight grid. These are what are called single instruction multiple data (SIMD) compute engines designed to do the polynomial math, twiddling, and other things that make up computing in FHE and to do them in parallel. An on-chip 2D mesh network connects the tiles to each other with wide, 512-byte, buses.

RELATED: Tech Keeps Chatbots From Leaking Your Data

Important to making encrypted computing efficient is feeding those huge numbers to the compute cores quickly. The sheer amount of data involved meant linking 48-GB-worth of expensive high-bandwidth memory to the processor with 819-GB-per-second connections. Once on the chip, data musters in 64 megabytes of cache memory—somewhat more than an Nvidia Hopper-generation GPU. From there it can flow through the array at 9.6 terabytes per second by hopping from tile-pair to tile-pair.

To ensure that computing and moving data don’t get in each other’s way, Heracles runs three synchronized streams of instructions simultaneously, one for moving data onto and off of the processor, one for moving data within it, and a third for doing the math, Golder explained.

It all adds up to some massive speedups, according to Intel. Heracles—operating at 1.2 gigahertz—takes just 39 microseconds to do FHE’s critical math transformation, a 2,355-fold improvement over an Intel Xeon CPU running at 3.5 GHz. Across seven key operations, Heracles was 1,074 to 5,547 times as fast.

The differing ranges have to do with how much data movement is involved in the operations, explains Mathew. “It’s all about balancing the movement of data with the crunching of numbers,” he says.

FHE Competition

“It’s very good work,” Kurt Rohloff, chief technology officer at FHE software firm Duality Technology, says of the Heracles results. Duality was part of a team that developed a competing accelerator design under the same DARPA program that brought forth Intel’s Heracles. “When Intel starts talking about scale, that usually carries quite a bit of weight.”

Duality’s focus is less on new hardware than on software products that do the kind of encrypted queries that Intel demonstrated at ISSCC. At the scale in use today “there’s less of a need for [specialized] hardware,” says Rohloff. “Where you start to need hardware is emerging applications around deeper machine-learning-oriented operations like neural net, LLMs, or semantic search.”

Last year, Duality demonstrated an FHE-encrypted language model called BERT. Like more famous LLMs such as ChatGPT, BERT is a transformer model. However it’s only one-tenth the size of even the most compact LLMs.

John Barrus, vice president of product at Dayton, Ohio–based Niobium Microsystems, an FHE chip startup spun out of another DARPA competitor, agrees that encrypted AI is a key target of FHE chips. “There are a lot of smaller models that, even with FHE’s data expansion, will run just fine on accelerated hardware,” he says.

With no stated commercial plans from Intel, Niobium expects its chip to be “the world’s first commercially viable FHE accelerator, designed to enable encrypted computations at speeds practical for real-world cloud and AI infrastructure.” Although it hasn’t announced when a commercial chip will be available, last month the startup revealed that it had inked a deal worth 10 billion South Korean won (US $6.9 million) with Seoul-based chip design firm Semifive to develop the FHE accelerator for fabrication using Samsung Foundry’s 8-nanometer-process technology.

Other startups including Cornami, Fabric Cryptography, and Optalysys have been working on chips to accelerate FHE. Optalysys CEO Nick New says Heracles hits about the level of speedup you could hope for using an all-digital system. “We’re looking at pushing way past that digital limit,” he says. His company’s approach is to use the physics of a photonic chip to do FHE’s compute-intensive transform steps. That photonics chip is on its seventh generation, he says, and among the next steps is to 3D integrate it with custom silicon to do the nontransform steps and coordinate the whole process. A full 3D-stacked commercial chip could be ready in two or three years, says New.

While competitors develop their chips, so will Intel, says Mathew. It will be improving on how much the chip can accelerate computations by fine-tuning the software. It will also be trying out more massive FHE problems, and exploring hardware improvements for a potential next generation. “This is like the first microprocessor…the start of a whole journey,” says Mathew.

Scientists don’t know much about how insects spend their time, but it’s well worth finding out. Insects play key roles in food webs and pollinate our crops, and social insects have a lot to teach us about the basics of friendship formation and communication. An ultralightweight radio-frequency tag designed to be worn by a paper wasp may help scientists get a glimpse at some basic behavioral information that’s long been missing: Where do the animals go when they leave the nest?

The tag is just 20 milligrams—about one third the weight of a drop of water. It was presented on 18 February at the IEEE International Solid State Circuits Conference in San Francisco by doctoral student Yi Shen, who works in the lab of University of Michigan electrical engineer David Blaauw. University of Michigan computer scientist Hun-Seok Kim developed localization algorithms to help spot the tag. Their challenge was to make an ultralightweight transmitter that had sufficient range (1.45 kilometers) and accuracy (0.9 meters) to locate these tiny insects.

They’re not the only ones trying to make more accurate, less intrusive trackers for small critters. Cellular Tracking Technologies (CTT) of Cape May, N.J., sells a 60-mg tracker that’s being used to follow the migration patterns of Monarch butterflies. This tracker uses photovoltaics paired with a capacitor and transmits a Bluetooth signal. Anyone can download an app to help track the butterflies. Other versions of the tracker are designed to be worn by nocturnal bats and are fitted with batteries. To track birds that move during the night as well as during the day, CTT makes systems that combine photovoltaics with a rechargeable battery.

What Wasps Want

But even 60 mg would weigh down a wasp. “Every animal that has been tracked is much bigger than a wasp,” says Elizabeth Tibbetts, who studies their behavior and evolution at the University of Michigan. Tibbetts advised Blaauw on their design.

Honeybees and butterflies get a lot of attention, but “people forget to love wasps,” Tibbetts says. Paper wasps are a gardener’s friend. These pollinators eat nectar and prey on caterpillars. And they don’t typically sting humans.

They also have complex social lives and can even recognize each other’s faces. Tibbetts says life is different when you know that one wasp is Diana and the other is Susan, as opposed to a life where “everyone is just another wasp.” Wasps form friendships and partnerships, though some are loners. When they come out of hibernation in the spring, aggregations of about 10 wasps hang out, fight, scope each other out, and decide which others to join up with in cooperative groups. Some decide not to join a group.

Tibbetts says she and other researchers have been able to watch these complex behaviors because wasps usually return to their nests. Wasp researchers identify individuals by putting colored dots on them. “We don’t know anything about what they do when they’re not at their nests,” she says. Sometimes they don’t come back. Did Susan die, start her own nest, or join up with a different nest? With the right kind of tracker, Tibbetts hopes to find out.

Paper wasps weigh about 125 milligrams. They can carry heavy loads, ferrying caterpillars back to their nests. But Blaauw and Shen sought to keep the tag as light as possible, so that the animals can forage freely. They also had to make sure it would not interfere with the wasp’s aerodynamics, so it needed to be small in addition to lightweight.

Brendan Casey

Getting the right combination of light weight, long range, and positional accuracy was key. Jettisoning the battery was the first step. “Batteries don’t scale,” says Blaauw. A miniaturized battery can’t provide enough current to generate a strong radio signal. Capacitors, which store energy by accumulating charges on surfaces, do better at small scales, Blaauw says. “Really small capacitors can store enough charge now to send a radio pulse,” he says. The capacitor used in the wasp tag weighs just 0.86 mg. A tiny photovoltaic array slowly charges up the capacitor until it has enough energy to generate a radio signal.

The need to aggressively miniaturize the entire system created constraints on the circuit design, Shen says. During transmission, the signal can interfere with other parts of the circuit, including the controller and oscillator. So these parts are isolated from the rest of the circuit during transmission. Blaauw says designing the circuit for a specific biological application led them to come up with new design ideas that would not have occurred to them otherwise. “This problem led us to circuit innovations,” says Blaauw.

Michael Lanzone, a behavioral biologist and CEO of CTT, says the wasp tag is impressive. “A tag that weight gives the rest of us something to push for,” he says.

The 9-square-millimeter tag is attached to circuit board for programming.Yi Shen and David Blaauw

Shen says since paper wasps are active only in the warmer months, the team rushed to test their transmitter on one of the pollinators in time to submit their work to ISSCC. In addition to circuit designs, they used CT scans of a wasp to make sure the tag would fit on the insect and would be unlikely to interfere with its aerodynamics. A collaborator in the biology department put on two pairs of gloves to block the creature’s stinger and affixed the tag. The team took the animal outside, and it rapidly flew out of sight while they tracked it for about a kilometer and a half. So far, so good. This summer, they hope to conduct more tests.

Lanzone says he hopes the University of Michigan technology gets funding and further develops the tag to get it in the hands of researchers. “There’s a lot of cool tech that comes out of university labs, but then you don’t hear about it again. I’m excited to see if they can expand it to the next level.”

“I hope this thing works—it’s going to be so fun to use on wasps,” says Tibbetts.

Your smartwatch can track a lot of things, but at least for now, it can’t keep an accurate eye on your blood pressure. Last week researchers from University of Texas at Austin showed a way your smartwatch someday could. They were able to discern blood pressure by reflecting radio signals off a person’s wrist, and they plan to integrate the electronics that did it into a smartwatch in a couple of years.

Beside the tried-and-true blood-pressure cuff, researchers in general have found several new ways to monitor blood pressure using pasted-on ultrasound transducers, electrocardiogram sensors, bioimpedance measurements, photoplethysmography, and combinations of these measurements.

“We found that existing methods all face limitations,” Yiming Han, a doctoral candidate in the lab of Yaoyao Jia, told engineers at the IEEE International Solid State Circuits Conference (ISSCC) last week in San Francisco. For example, ultrasound sensing requires long-term contact with the skin. And as cool as electronic tattoos seem, they’re not as convenient or comfortable as a smartwatch. Photoplethysmography, which detects the oxygenation state of blood using light, doesn’t need direct contact, and indeed researchers in Tehran and California recently used it and a heavy dose of machine learning to monitor blood pressure. However, these sensors are thought to be sensitive to a person’s skin tone and were blamed for Black people in the United States getting inadequate treatment during the COVID-19 pandemic.

The University of Texas team sought a noncontact solution that was immune to skin-tone bias and could be integrated into a small device.

Continuous Blood Pressure Monitoring

Blood pressure measurements consist of two readings—systole, the peak pressure when the heart contracts and forces blood into arteries, and diastole, the phase in between heart contractions when pressure drops. During systole, blood vessels expand and stiffen and blood velocity increases. The opposite occurs in diastole.

All these changes alter conductivity, dielectric properties, and other tissue properties, so they should show up in reflected near-field radio waves, Jia’s colleague Deji Akinwande reasoned. Near-field waves are radiation impacting a surface that is less than one wavelength from the radiation’s source.

The researchers were able to test this idea using a common laboratory instrument called a vector network analyzer. Among its abilities, the analyzer can sense RF reflection, and the team was able to quickly correlate the radio response to blood pressure measured using standard medical equipment.

What Akinwande and Jia’s team saw was this: During systole, reflected near-field waves were more strongly out of phase with the transmitted radiation, while in diastole the reflections were weaker and closer to being in phase with the transmission.

You obviously can’t lug around a US $50,000 analyzer just to keep track of your blood pressure, so the team created a wearable system to do the job. It consists of a patch antenna strapped to a person’s wrist. The antenna connects to a device called a circulator—a kind of traffic roundabout for radio signals that steers outgoing signals to the antenna and signals coming in from the antenna to a separate circuit. A custom-designed integrated circuit feeds a 2.4-gigahertz microwave signal into one of the circulator’s on-ramps and receives, amplifies, and digitizes the much weaker reflection coming in from another branch. The whole system consumes just 3.4 milliwatts.

“Our work is the only one to provide no skin contact and no skin-tone bias,” Han said.

The next version of the device will use multiple radio frequencies to increase accuracy, says Jia, “because different people’s tissue conditions are different,” and some might respond better to one or another. Like the 2.4 GHz used in the prototype, these other frequencies will be of the sort already in common use such as 5 GHz (a Wi-Fi frequency) and 915 megahertz (a cellular frequency).

Following those experiments, Jia’s team will turn to building the device into a smartwatch form factor and testing them more broadly for possible commercialization.

It’s no secret that demand for AI hardware has increased demand for computer memory. Industry analyst TrendForce expects the contract price for memory to increase by up to 95 percent in the first quarter of 2026, and that comes after similarly aggressive changes through the second half of 2025.

The burden of the surging price has fallen with particular weight on low-cost computing companies like Raspberry Pi. The Raspberry Pi 5, with 16 gigabytes of RAM, has nearly doubled in price from US $120 in November 2025 to $205 today. Framework, a company that makes highly configurable and repairable laptops, has announced two rounds of memory price hikes. Others, such as Orange Pi, have made no official comment, but the price of an Orange Pi 5B with 16 GB of RAM has surged from $160 at the start of 2025 to $312 today.

“If you have a product that’s relatively low cost, the memory is going to be a relatively large portion of it,” says Raspberry Pi CEO Eben Upton. Most Raspberry Pi computers of a particular model have the same board design and the same hardware components—except for the memory, which can be upgraded to suit the user’s needs. With little else to differentiate them, Raspberry Pi has to pass increased memory costs on to customers.

A Perfect Storm Threatens Low-Cost Computing

The situation is worsened by the way memory is produced. “Generally, you have a single fungible pool of manufacturing capacity in DRAM that you can use to do anything. It can be used to make commodity DRAM, DDR, LPDDR, or you can use it to make HBM [the type most commonly used for AI hardware],” explains Upton.

That means low-cost computer manufacturers are competing for the same pool of manufacturing capacity as AI hardware giants. And with the world’s most valuable tech companies spending billions on AI infrastructure, low-cost computer manufacturers have little hope to negotiate the price.

Larger computer manufacturers can mitigate the memory price shock by negotiating larger or longer contracts in exchange for lower prices, or by tolerating a lower profit margin. Others are rumored to have stocked up on memory as prices surged.

RELATED: How and When the Memory Chip Shortage Will End

But these strategies aren’t available to companies that sell computers at low price points or in lower volumes. The lower price of these computers means there’s not much margin to absorb a price increase. Companies like Raspberry Pi also purchase in lower volumes, which means it’s difficult to negotiate a volume discount.

It’s a perfect storm for low-cost computing and one that, in contrast to 2025’s U.S. tariff hikes, has led to immediate and unavoidable problems. While tariffs did place some pressure on price for low-cost computers, that pressure wasn’t uniformly felt. Raspberry Pi, which manufactures its computers in the United Kingdom, found itself in a better position than those that manufactured in China. The memory price increase, on the other hand, applies to all companies in this industry, no matter where or how manufacturing takes place.

Price Increases With a Side of Reduced Memory Capacity

Companies that build PCs with removable memory are turning toward a bring-your-own-memory approach. Framework offered this option before memory prices increased, but several specialty desktop manufacturers have recently announced similar bring-your-own-RAM options. However, this isn’t possible for many low-cost computers, including those from Raspberry Pi, because they solder the memory to the mainboard.

Instead, Raspberry Pi is using a different strategy. A new iteration of the Raspberry Pi 4 Model B moved from a single memory module to a dual-module configuration. “As you can generally buy smaller RAM more easily than larger RAM, we can use a pair of back-to-back modules instead of a single larger one. You have more vendor diversity, more vendor flexibility,” Upton says. He expects the current pricing will remain the same, but the change provides more options when looking to source memory in the future.

Of course, there’s another strategy all low-cost computing companies can use. They can simply offer less memory.

Raspberry Pi introduced a version of the Raspberry Pi 5 with 1 GB of RAM in December 2025. It debuted at $45 and was the only Raspberry Pi 5 model to avoid the February price increase. Raspberry Pi was among the first to do this, and in retrospect the decision looks like the canary in the coal mine.

Analysts predict that price-constrained devices, such as budget smartphones, will soon be forced to cut memory or raise prices (and possibly both). While this has yet to happen with brands well known in North America, there are hints of it in budget phones from brands that are popular internationally. Poco recently added a less expensive 4-GB version of the M7 Plus 5G smartphone and the new Honor X6d smartphone will ship with 4 GB of memory to start, a downgrade from the preceding Honor X6c, which had 6 GB. Both Poco and Honor are based in China.

So, when will memory prices come down or, at least, stop rising?

Upton expects the timing to be similar to past memory price cycles, which means it’s likely to last for at least a few years. “Memory will be expensive this year. It will probably be expensive next year,” he said, adding that he’d be “a little bit surprised” if price increases have not leveled off into 2028. In any case, he cautioned against being too sure of the future. During the chip shortage of 2021 through 2023, companies and consumers worried that inexpensive logic chips were a thing of the past, but the situation eventually returned to normal. “Like all bubbly phenomena, it’s very hard to measure.”