Cadence IP

Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 04 Aug 2011 00:00:00 GMT

Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI Express Gen3 Controller IP advanced capabilities, with a discussion on Single Root I/O Virtualization (SR-IOV). Part 1 was covered in a recent blog post.

What is SR-IOV? Briefly, SR-IOV is a specification that allows a PCIe device to appear to be multiple separate physical PCIe devices. PCI-SIG created and maintains the SR-IOV specification with the goal of having a standard specification to help promote interoperability. One of the milestones achieved for Cadence’s design IP for PCI Express Gen3 is proving SR-IOV interoperability in silicon against an Intel chipset.

Why is it important? The two main advantages of an SR-IOV PCIe device are:

It allows multiple OS’s to have their own private view of the PCIe device
It helps improve I/O performance by reducing latency of the hypervisor

How have Cadence customers used PCI Express Gen3 SR-IOV to solve their design problems? In one example, a SAS RAID controller using 2 physical functions (PFs) and 16 virtual functions (VFs) was able to have 16 guest applications privately access the PCIe device. VFs are “lightweight” and have the advantage of requiring significantly less logic overhead than PFs.

Please see the video below for more details. Also, please comment on how you've seen PCIe Gen3 SR-IOV used in different applications.

Stella Murphy

Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 28 Jul 2011 18:00:00 GMT

This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser. In part one, Ashwin Matta, Cadence engineering director, discusses the IP performance and core capabilities of the Cadence PCI Express Gen3 IP captured by the display trace.

Highlights:

The Cadence PCI Express 3.0 design IP complies with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification
The demo shows Cadence's PCIe Gen3 high performance x8 configuration operating at full speed 500Mhz clock rate with a transfer rate close to 8GT/s
The display trace shows the PCIe Gen3 IP transition from Gen1 speed 2.5 GT/s to Gen3 8GT/s
LTSSM flow graph showing equilibrium between upstream and downstream packet transfers and speed of operation at 8GT/s

Please come back soon to view Part 2 of 2 showing the advanced features of Cadence's PCI Express Gen3 IP.

Stella Murphy

Cadence Demonstrates PCI Express 3.0 Controller IP in Customer Silicon

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 30 Jun 2011 19:00:00 GMT

At the June 2011 PCI-SIG Developer's Conference, Cadence demonstrated Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration in a customer's ASIC. The Cadence PCI Express 3.0 controller in the ASIC reference card was attached to a LeCroy Summit T3-16 analyzer and Summit Z3-16 exerciser platform to demonstrate the Cadence PCI Express 3.0 core with traffic running at 8 GT/s per lane.

The Cadence PCI Express 3.0 design IP complies with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification.The PCI Express Gen3 IP successfully implemented in silicon advanced capabilities like Single-Root I/O Virtualization (SR-IOV), as well as the latest engineering change notices (ECNs) including ID-based Ordering, Re-Sizeable BARs, Atomic Operations, Transaction Processing Hints, Optimized Buffer Flush/Fill, Latency Tolerance Reporting and Dynamic Power Allocation. The Cadence PCI Express 3.0 IP has already been implemented in the recently announced PMC-Sierra 6Gb/s SAS Tachyon protocol controller.

To learn more about the Cadence Design IP for PCI Express Gen3 IP, please come back next week to see the PCI Express Gen3 IP video of the demonstration.

Stella Murphy

Can DRAM Contents Survive a Reboot? Surprisingly, In Most Cases The Answer is, “Yes”

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 20 Apr 2011 17:00:00 GMT

A Cadence DRAM Memory Controller IP customer asks, "I have a DRAM subsystem with ECC and my system has the capability to use write data masks and partial-word writes. DDR3 has a reset pin, why can't I just reset it? Why do I need to initialize the memory?"

The answer is "yes, you must initialize it" but the reason may be surprising to many people: DRAM contents are not lost when the power is turned off! I stumbled upon this great research paper from Princeton University this week which is interesting in itself (it talks about how most encryption is vulnerable to hacking through the DRAM), but also has some interesting data about just how long data can persist in DRAM. The researchers found that some of the bits in DRAM were still capable of holding charge minutes after losing power, even when the memory is removed from the machine entirely. A video clip located here shows the process they used, and at one point shows them removing a DIMM from one machine and putting it into another - and then retrieving all the data out of that DIMM!

For those interested in information technology security, this data suggests the importance of encrypting the contents of DRAM as well as the contents of a hard drive - but that was not the concern of the customer who asked the original question. When using ECC (Error Correcting Codes) in DRAM, a typical arrangement is to have 64 bits of data and 8 extra ECC bits that hold a SECDED code that is capable of correcting a one-bit error and detecting a 2-bit error in the 64 bits of data (Cadence's DRAM controller allows other sizes like 32&7, 32&4, 16&2 but let's stick with 64&8 for now).

The problem arises when the system needs to write less than the full 64 bits of data, and the memory controller needs to do a Read-Modify-Write (RMW) operation on the memory location to be able to preserve the part of the write data that was previously in that memory location that is not being overwritten by the current write operation. If the 64 bits of data that are being partially overwritten have stale and partially-degraded memory contents from the previous time the DRAM was used (for example, if the machine was turned off momentarily and then turned back on again) then when the memory controller tries to read that memory location it will encounter ECC errors when it tries to do the read portion of the RMW operation.

Wait a minute, don't newer DRAMs like DDR3, DDR4 and LPDDR2 have a reset pin?

Yes they do - but that reset only resets the memory state machines; it is not guaranteed to reset (or not reset) the memory contents.

Umm... okay, so what do I do about it?

I'm glad you asked! The simplest thing is never to do masked or partial word writes - then any time you might use a memory location that had old data in it, you will overwrite it completely. You system will still have lots of errors, though, if you happen to read a location in memory that has not been written to yet. This solution is impractical for systems working with short and irregular data packets like networking and video.

In simulation, you can use advanced properties of your Verification IP (VIP) such as Cadence's VIP Catalog Memory Models (formerly known as Denali MMAV) to set a pre-assigned value into all the DRAM when you start simulations, so that you don't have to initialize the DRAM in simulation every time. Just be sure to do your final signoff on a memory with randomly assigned background data and do take care to initialize it.

For your real system, you can write a program for your CPU that writes to every DRAM location, although this could take a while. Cadence's DRAM Memory Controller IP has a BIST option that will run a hardware test on the DRAM as well as leave the DRAM's ECC check bits in a correctly calculated state and which will run significantly faster than in software.

Now... how do I encrypt that DRAM?

Maybe a topic for another blog...

Marc Greenberg

New Memory Technologies, New Possibilities

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 11 Apr 2011 15:30:00 GMT

As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory and storage subsystem is now central to SoC Realization. Poor memory and storage design will impact everything from the user experience to the applications that are possible. There is nothing quite so sad as a shiny new gadget that falls short because of poor memory performance (something easily avoided with the right IP), or trying to install a new app only to have to decide what you must delete to make room for it.

It’s been a busy few weeks for the IP team with the announcement of support for two new memory technologies – DDR4 and Wide I/O.

With Wide I/O and DDR4 offering significantly improvements for the device classes they target for, it’s exciting to contemplate how design teams will leverage them to deliver on the next wave of devices. So whether it’s a high performance gaming desktop, a sleek new tablet, or enterprise equipment that interests you, new memory technologies will play a key role.

Learn more about Cadence Design IP for Memory and Storage.

Neil Hand

The 3D SSD

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 29 Nov 2010 23:22:27 GMT

You need three things from a solid-state disk (SSD): speed, capacity, and reliability.

You need three things from a portable SSD: speed, capacity, reliability, and diminutive size. And you can’t get much smaller than packing an SSD into the form factor of a USB memory stick. That’s exactly what LaCie has done with its FastKey drive. It’s packed a 30 to 120Gbyte USB 3.0 SSD into the form factor of a slightly oversized USB memory stick but the LaCie FastKey doesn’t perform like a memory stick. Depending on capacity, the read/write speeds of the LaCie FastKey are 210/70 to 260/180 Mbytes/sec. Add in 64Mbytes of DRAM cache and 256-bit AES encryption and you’ve got one Hulk of a memory stick.

Now I don’t know this for a fact, but it seems to me that you can’t build a product like this with conventional IC packaging. The volumetric allowances argue for more of a 3D chip assembly approach. And whether or not this particular product employs 3D assembly, the existence of the LaCie FastKey points the way to a future where the innards of many such memory-stick SSDs will make use of 3D assembly. After all, plastic IC packaging really adds no value to this sort of product and merely gets in the way.

Increasingly, 3D assembly is going to become a competitive advantage when the end product’s size matters. It already matters in mobile phone handset design and 3D assembly is widely used in this niched (but very large) market segment. As time unwinds, 3D assembly techniques will improve and get less costly because of high-volume mobile handset market demands. The rest of the industry will follow.

STT-MRAM -- from Seagate???

denali_mktg@cadence.com (Denali Software, Inc.) — Fri, 05 Nov 2010 16:58:03 GMT

On June 12, 1989, I flew to Minnesota from Denver, Colorado, picked up a rental car, and drove from Minneapolis to Bloomington to attend a special disk drive conference being held by the leading vendor of cutting-edge 5.25-inch hard disk drives--Imprimis--which was the disk-drive spinout subsidiary of Control Data Corporation (CDC). I had an ulterior motive on this trip: to get two of Imprimis’ 330Mbyte SCSI disk drives for my EDN “All Star PC Project.” The Imprimis drives were the biggest, baddest hard drives available at the time and Imprimis had a world-class lead in high-speed drive design attributable to CDC’s world-class magnetics research center in Bloomington. Unfortunately, June 12, 1989 was also the day that CDC announced Seagate’s purchase of Imprimis and the addition of Imprimis' magnetics research facility to Seagate’s growing technology arsenal. So I arrived at Imprimis to find the conference cancelled and no one to speak with. I left the Imprimis lobby to fly back to Colorado within an hour of my arrival at Imprimis, without the drives. (I did eventually get a pair of those drives for the All Star PC project, but that’s a story for another time.)

Fast forward to 2010--this week in fact. I’m at the 8th International SoC Conference in Newport Beach, California and I’ve just heard a presentation from Seagate’s VP of the Memory Products Group R& D team Pat Ryan. His topic: spin-transfer-torque magnetic RAM (STT-MRAM). This R& D group is part of the Minnesota magnetics research group that Seagate bought 21 years ago and that facility is just celebrating its 50th year of existence.

Despite having written several detailed articles about MRAM and STT-MRAM, I had no idea that Seagate had a team working on the technology, but it makes sense. The fundamental memory cell in an MRAM, STT or otherwise, is the magnetic tunnel junction (MTJ) and it turns out that MTJs are very familiar to disk drive vendors. “We make millions per day,” said Ryan, “to serve as read/write heads in disk drives.” The company has devoted some resources to investigating the use of MTJs in STT-MRAM.

It turns out that Seagate knows a lot about STT-MRAM and MTJs.

Researchers at the company know how to make thin anisotropic magnetic films that allow magnetic polarization that’s perpendicular to the junction, which improves storage stability. They also know how geometric scaling affects read and write currents for STT MTJs. They have put lots of read/write cycles on STT MTJ memory cells and know that the MTJ’s storage abilities do not degrade with extended cycling. They also know that the memory retention is well hardened against external fields and radiation.

Finally, they know that STT MRAM will be giving embedded SRAM, DRAM, and NOR Flash a run for the money starting around the year 2013.

But don’t look for Seagate to be a player in the STT MRAM IC competition. Ryan gave the clear impression that Seagate is currently only interested in enhancing hard-disk drive performance. It will leave the IC race to others.

Apple boots HDD--completely out of the new MacBook Air notebooks. SSD is the only option

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 21 Oct 2010 16:42:42 GMT

Claiming that the move unifies Apple’s product line, Steve Jobs yesterday announced two new lightweight MacBook Air notebook computers. Significantly, neither HDD nor optical disk storage is an internal option for these two new laptops. SSD is the only storage on offer, with capacities from 64 to 256 Gbytes. Although Jobs claims that Apple placed the SSD “right on the motherboard,” the images he showed were of a small circuit board (clearly NOT a standard SSD board format) that plugged into the motherboard. Elements of the announcement that make the new MacBook Airs more resemble an iPad include multi-touch gestures on a generous touchpad below the full-size keyboard, a Mac-specific app store, an app home screen, full screen apps, auto save, and apps that resume when launched.

Here’s more coverage at MSNBC.com’s Techblog: http://technolog.msnbc.msn.com/_news/2010/10/20/5322959-live-coverage-apple-reveals-macbook-air-mac-os-x-lion-ilife-11-and-more

Angelbird Ltd. Introduces “Wings,” a low-cost PCIe SSD for PCs. $239 for 16 Gbytes

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 19 Oct 2010 18:34:14 GMT

Stop me if you’ve heard this one. The fastest way to get high performance from an SSD is to bypass the disk interface and plug the SSD directly into the PC’s PCIe port. Vendors of high-performance (read “expensive”) SSDs do just that. So just where does startup (or is that “upsart”) Angelbird Ltd. get the moxie to announce a PCIe-based SSD card that sells for $239? The card is called “Wings” and is said to boot on PCs and Macs. For $239, you get a base card with 16 Gbytes of NAND Flash storage. A second version of the card with 32 Gbytes of SSD is also offered. Both cards implement a 4-lane version of PCIe. However, the really innovative feature of the Wings PCIe SSD card is that it acts as a carrier for as many as four add-on SSDs. The add-on cards look like SATA drives minus the aluminum case and they plug into four sockets on the PCIe carrier card. With four drives snapped into place, the Wings card delivers peak read/write speeds of 1081/945 Mbytes/sec.

Hitachi-LG Data Storage fixes optical drive with SSD assist to use one SATA port

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 19 Oct 2010 00:04:10 GMT

Hitachi-LG Data Storage has updated the hybrid optical/SSD drive it announced earlier this year (How does a hybrid SSD/optical drive make sense?) by integrating the SSD with the optical drive controller and making both the optical and solid-state drives accessible through one 6Gbps SATA III port. The first-generation drive introduced earlier this year at the Computex electronics show in Taipei was essentially an SSD tacked onto and stuffed into the same case as an optical disc drive. The result was two separate drives, each with its own SATA port. The new drive fully integrates the optical drive and SSD onto one circuit board that share a common 6Gbps SATA III connector.

Made in South Korea: Graphene memristor memory cells on a flexible plastic substrate

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 14 Oct 2010 17:53:20 GMT

IEEE Spectrum has just reported on the successful fabrication of graphene-based memory cells on a flexible plastic substrate by Sung-Yool Choi and his research team working at the Electronics and Telecommunications Research Institute in Daejeon, South Korea. The memristor memory closely resembles that of HP, using a simple crosspoint-array interconnect, with a memory cell made of graphene oxide instead of HP’s titanium oxide at each crosspoint. In both cases, the memristor effect results from the force of an electric field that pushes oxygen atoms back and forth within the memory cell. The experimental graphene cells measure 50 microns, so they’re more than 1000 times larger than those developed by HP, but the graphene cells are made with a much simpler, non-IC process technology and the cells are deposited on flexible plastic, which opens the technology up to many, many interesting--and potentially low-cost--uses.

You’ll find the IEEE Spectrum article here.

More Memristor articles in the Denali Memory Report:
The 6-minute video guide to memristors (must-see video)
HP’s memristor finds a commercial semiconductor vendor: Hynix

Rice University reports that silicon oxide also good for memristors
Rice U’s silicon-oxide memristor more phenomenon than device, for now

Brian Fuller @EETimes: Renesas to put MRAM in 90nm microcontrollers by 2013

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 13 Oct 2010 20:05:15 GMT

EETimes’ Brian Fuller is blogging live from the Renesas DevCon down in southern California and he reports this morning that Renesas has announced plans to incorporate MRAM (magnetic RAM) in its microcontrollers built using 90nm process technology, with parts to be introduced by 2013. At that geometry, Renesas expects the MRAM to support 150MHz operation. Two years later using 40nm process technology, Renesas expect to hit 200MHz.

Conceptually, MRAM is well suited to use in microcontrollers because it’s fast like DRAM and nonvolatile like Flash but doesn’t have the write-cycle limitations of Flash. If Renesas pulls off this feat of manufacturing, its microcontrollers will be able to employ “unified memory.” Only one type of memory with one address space and only one type of memory access protocol is needed to satisfy all of the on-chip storage needs of the microcontroller. Although there are a few small MRAMs on the market, the technology has not yet moved into the commercial mainstream. If it does, it will welcome back magnetic storage--which was king of the hill from the 1950s through the mainframe and minicomputer eras and then banished to obscurity in the early 1970s when DRAMs first appeared.

MRAM is one of several “new” memory technologies vying to displace DRAMs and Flash memory. Others include PCM (phase-change memory) and memristor-based memory, which Hynix just licensed from HP for potential future commercial production. Hynix is calling memristor-based memory ReRAM, for “resistive RAM.”

Sandforce Enterprise-Class SSD 2500/2600 processors deliver double performance

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 11 Oct 2010 15:51:08 GMT

SandForce has just announced a new enterprise-class SF-2000 SSD processor family including the SF-2500 and SF-2600, which deliver approximately twice the performance of the company’s existing SF-1500 SSD processor. The new SSD processors start with SATA III 6Gbps host interfaces that have twice the maximum bandwidth of the SF-1500’s SATA II interface. Maximum sequential read/write performance is now rated at 500/500 Mbytes/sec, up from 260/260 Mbytes/sec, and maximum read/write IOPS performance is also doubled from 30K/30K to 60K/60K. The new SSD processors support more and faster Flash memory interfaces as well: async, Toggle-Mode, and ONFi2 at transfer rates as fast as 166 Mtransfers/sec. ECC protection is boosted to accommodate 30nm- and 20nm-class Flash devices, up from 24 bits per 512 bytes to 55 bits per 512 bytes. Encryption capability has also been boosted to 256-bit AES, plus support for the existing 128-bit AES encryption.

Anandtech reports that Intel’s new SSDs that incorporate 25nm Flash will have 4x the lifespan rating

denali_mktg@cadence.com (Denali Software, Inc.) — Fri, 08 Oct 2010 01:09:18 GMT

This blog previously reported that Intel will be rolling out new versions of its highly regarded X25-M SSDs. These new drives will incorporate 25nm MLC Flash devices. Now, Anandtech has reported some interesting specs. Maximum capacity is up from 160 to 600 Gbytes. Sequential read performance is unchanged at 250 Mbytes/sec but write performance will jump from 100 to 170 Mbytes/sec and the read/write IOPS ratings jump from 35K/80.K to 50K/40K. Perhaps the biggest surprise is a quadrupling of drive lifespan, from 7.5-15 Tbytes to 30-60 Tbytes for 4Kbyte random writes. One thing that’s not going to be upgraded is the 3Gbps SATA interface.

Renesas introduces new 1.1Gbit low-latency DDR DRAM (LLDRAM) for networking apps

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 04 Oct 2010 16:53:30 GMT

Renesas has introduced a new 1.1Gbit, low-latency DDR DRAM (LLDRAM) primarily for networking applications that really need the device’s low 13.3nsec read/write latency. This part is another in the series of LLDRAMs originally developed by NEC. (Renesas and NEC announced a merger agreement last September and have now completed this action.) There are four devices in the 1.1Gbit LLDRAM family: the µPD48011318FF, the µPD48011336FF, the µPD48011418FF, and the µPD48011436FF. the first two devices have burst lengths of 2 and the second two devices have burst lengths of four. Devices ending in 18FF are organized as 64M-by-18-bit DRAMs and the devices ending in 36FF are organized as 32M-by-18-bit DRAMs. Devices with a burst length of 2 have a maximum DDR transfer rate of 600Mtransfers/sec and devices with a burst length of 4 have a maximum DDR transfer rate of 800Mtransfers/sec.

LLDRAMs are fairly specialized, low-volume devices and as a consequence, per-bit costs are substantially higher than for mainstream PC-centric DDR SDRAMs. However, LLDRAMs don’t’ really compete with DDR SDRAMs, they compete against SRAM, which is the real alternative for applications that require low-latency memory. You can read more about low-latency DRAMs in this Denali Memory Report blog entry from last year (“Low Latency DRAMs Continue to Serve Networking Niches”).

Also, if you’re interested in the specialized memory needs of high-speed networking applications and if you’re a customer of LSI Corp, I’m moderating a panel on memory for networking applications at LSI Corp’s Conference and Technology Showcase being held this week in Milpitas, CA.

OCZ invents proprietary 20Gbps link for SSDs, snubbing SAS, SATA, and PCIe

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 30 Sep 2010 18:29:37 GMT

Yesterday, OCZ released a curious statement saying that it was unveiling a proprietary interface it's calling the “High-Speed Data Link” (HSDL) to accelerate connection to solid-state storage. The company is apparently unsatisfied with existing interface options (SAS, SATA, PCIe) and has developed HSDL to eliminate I/O bottlenecks and enable SSD technology to operate at its full potential. One HDSL can operate at transfer rates as fast as 20Gbps and multiple channels can be ganged for even higher transfer rates. The announcement also reveals an upcoming SSD to be called “IBIS” that will make use of the HDSL interface. Each IBIS drive will ship with single-port HDSL adapters and the company also plans to offer multiport adapters for systems that need multiple drives and more bandwidth. OCZ says it’s making HDSL an open standard and hopes to attract other vendors’ support for the high-speed storage interface.

Elpida announces 30nm, low-voltage, low-power, 2Gbit DDR3 SDRAM with TSV (through silicon via) 3D option

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 30 Sep 2010 18:09:27 GMT

The headline pretty much says it all. Memory vendor Elpida hit all the DRAM high notes in its most recent announcement of a new 30nm DDR3 SDRAM. First, Elpida says in one place in the press release that it will produce this SDRAM with a “30nm-level” process. However, most of the announcement doesn’t qualify “30nm” with “level” so this may well be a true 30nm process technology, which makes this quite advanced for an SDRAM process technology and ahead of other announces SDRAM production process technologies. For system designers, however, what’s important is that the 30nm process will produce SDRAMs that run on 1.35V, consume 15% less operating power and 10% less standby power than the company’s 40nm SDRAMs, and these SDRAMs can meet the DDR3-1866 transfer rate (although not at 1.35V). At 1.35V, the SDRAMs' operation is “limited” to DDF3-1600.

One really notable part of the Elpida announcement is its mention of 3D assembly using TSVs (through silicon vias). The Elpida release says: “The company also plans to use the process together with Through Silicon Via (TSV) technology to support one-chip memory solutions for mobile phones, digital still cameras and PC DRAMs.” Of course, the producers of high-volume mobile and consumer products are already using 3D chip packaging, but mostly rely on wire bonds to connect the stacked chips. A 3D assembly process based on TSVs promises a host of benefits including faster interchip I/O rates, lower operational power, less heat, and even lower assembly costs (at least eventually). So the inclusion of this mention in an SDRAM press release is really more significant than it may seem at first glance. However, system designers only realize these benefits when the chips are designed for TSVs--thus the importance of including this information in this announcement.

LSI Corp to host IC innovation conference and technology showcase in Milpitas next week

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 30 Sep 2010 00:33:35 GMT

On October 5 through 7, LSI Corp will be hosting a conference and technology showcase in at the beautiful Crowne Plaza Hotel in suburban Milpitas, just north of San Jose. Allow me to especially point you to two interesting panels. The first is on 3D ICs, which is a topic that just keeps getting hotter. Sure, it’s a high-volume technology, but it has fascinated vendors up and down the food chain for decades and it seems that the technology’s time has now come thanks to the Lilliputian dimensions and corresponding component requirements of today’s mobile devices. That panel takes place on Wednesday at 1:30 pm.

Immediately following at 2:45 pm is a panel on the critical memory needs of networking ICs. Not many applications bang on memory the way like high-speed networking and this panel will cover the issues, today’s answers, and future directions as only Brocade, Cisco, Infinera, LSI, TSMC, and Memoir Systems can define them. By the way, I’m moderating this panel because I’m the author of the Denali Memory Report blog (http://www.denali.com/wordpress/) so I can assure you that this is going to be one excellent panel.

LSI’s event is open to anyone interested in LSI Corp’s new ASIC and standard product solutions, except for LSI’s competitors of course. If interested, check out www.lsi.com/AI-conference for registration details but hurry because seating is limited. I hear they’re giving away some iPads too, but please don’t attend just for that. There’s also lunch.

New Blog: EDA360 Insider, for anyone involved with any aspect of system design

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 27 Sep 2010 23:21:51 GMT

I’ve just started a new blog called the EDA360 Insider (http://eda360insider.wordpress.com/). It’s about the ins and outs of system design from a Cadence insider’s perspective. I’ll be covering topics associated with the three key facets of system design according to the EDA360 vision document: System Realization, SoC Realization, and Silicon Realization. If you’re involved in any form of system design, you might want to take a look. Thanks.

Samsung rolls 8Gbyte DDR3 SODIMM, Dell picks it up immediately, stuffs four into 17-inch mobile workstation

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 27 Sep 2010 16:52:56 GMT

Samsung has announced that it is now shipping 8Gbyte DDR3 SODIMM SDRAM modules for high-end laptops that can accommodate that much memory. The modules are based on Samsung’s 40nm SDRAMs. (As noted previously, Samsung just announced production of 36nm SDRAM chips.) Many laptops aren’t designed to accommodate that much RAM, but Dell’s Precision M6500 mobile workstation can accommodate as many as four of these modules, for a total RAM capacity of 32 Gbytes. The Dell Precision M6500 has a 17-inch display, so it’s on the large side for a laptop PC. Dell is also placing two of these modules in its 15-inch Precision M4500 mobile workstation.

DRAMeXchange ranks NAND Flash vendors for Q210. Samsung wins, again.

denali_mktg@cadence.com (Denali Software, Inc.) — Fri, 24 Sep 2010 17:32:34 GMT

Last month, DRAMeXchange published rankings for the top “branded” NAND Flash vendors. No surprise, Samsung remains in the lead, selling almost $2 billion worth of NAND Flash chips during the quarter in a market that DRAMeXchange estimates as a $4.776 billion market. With those sales, Samsung pushed its market share just above 40%. Toshiba was in second place with a bit more than $1.5 billion in sales, for a 33% share. So between the #1 and #2 players, we see almost three-quarters of the NAND Flash market. Micron’s third with about 12% followed by Hynix and Intel. The market grew nearly 10% from 1Q09 to 1Q10.

Three of the end products clearly driving this sales growth for NAND Flash are the rising popularity of smart phones; the smash success of pad-like tablets, namely Apple’s iPad since competitors are only just now starting to appear (but when they come fully on line, watch out); and the rise in ebook reader consumption mainly driven by Amazon’s Kindle. These three application-driven product categories ensure a healthy, growing market for NAND Flash.

You can see all of DRAMeXchange’s numbers for 2Q10 here.

Note: Here’s a very informative video teardown of a Kindle 3 reader from Australia’s EE phenom Dave Jones:

JEDEC launches new SSD reliability standards, plans in-depth SSD tutorial in San Jose, October 5

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 23 Sep 2010 19:55:39 GMT

An article in ComputerWorld reports that JEDEC (www.jedec.org) has just announced two new standards for evaluating SSD performance and reliability: JESD218 Solid-State Drive (SSD) Requirements and Endurance Test Method and JESD219 Solid-State Drive Endurance Workloads. JESD218 defines SSD requirements including conditions of use and corresponding endurance verification requirements. SSD endurance should be rated using standard use conditions for the appropriate SSD class, but the JEDEC standard also establishes requirements for additional use conditions as agreed to between manufacturer and purchaser. JESD219 defines workloads for the endurance rating and endurance verification of SSD application classes and is used along with JESD218. You can download both standards from the JEDEC site, if you’re a member.

You might also be interested in an SSD tutorial JEDEC is sponsoring on October 5 at the Hyatt Regency Santa Clara. The tutorial features an in-depth technical session facilitated by Alvin Cox, a senior engineer with Seagate Technology and Chairman of JEDEC's JC-64.8 Subcommittee for Solid State Drives, and Steffen Hellmold, Vice President, Business Development with SandForce. The tutorial costs $175 for JEDEC members and $200 for non-members.

Crucial SSDs hit $1/Gbyte, with a crucial caveat

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 23 Sep 2010 16:48:18 GMT

The Bright Side of News (BSN, www.bsn.com) Web site reports today that Crucial is selling its M225 drives for $1/Gbyte (256Gbytes = $256) but there’s a catch or two depending on your perspective. First, the BSN site points out that these are MLC drives and implies that they’re not the world’s fastest SSDs but Crucial’s 256Gbyte M225 drive has a rated read/write speed of 250/200 Mbytes/sec, which is not a shabby speed rating at all. An internal 64Mbyte DRAM buffer no doubt helps in that department. Second, and perhaps more important, these are refurbished drives. What “refurbished” means in the context of an SSD is anyone’s guess and is not clarified by Crucial's Web store listing.

Top 10 SSD benefits: Samsung publishes list

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 22 Sep 2010 17:49:56 GMT

Samsung, SSD vendor and the world’s leader in Flash memory, has just published a list of the top 10 benefits of using SSDs. Here they are, somewhat tongue-in-cheek and unedited.

1. Speed Up Your Boot-Up: SSD knows that «go» means «go». Just turn it on and begin working in less than 30 seconds.

2. Zip through File Searches: Remember the last time you attempted a simple e-mail search using a Hard Disk Drive (HDD)? Now imagine crunching that time so it's 5x faster. That's the power of an SSD.

3. Trim File Transfer Time by Almost a Third: Transfer and copy files thirteen minutes and five seconds faster than usual--just enough time to give you a head start on rush-hour traffic.

4. Start Applications in Seconds: Need to make a quick ten-second edit before meeting with a client? SSDs load programs such as Adobe Photoshop and PowerPoint more than twice as fast as their HDD counterparts.

5. Double File-Compilation Power: Just because programmers sit behind a computer screen all day doesn't mean they're immune to slowness. An SSD boasts 2x faster file-compilation times than HDD.

6. Cut Downtime by Half: Routine maintenance tasks shouldn't disrupt your work flow. SSD cuts simple tasks such as virus scans by almost 50 percent.

7. Reduce Power Consumption: SSD requires less energy than a conventional HDD and can add an average of 30 minutes to battery life.

8. Master Multitasking: SSD smoothly handles multiple programs so you can crop photos and load game maps nearly 3x faster than with HDD.

9. Cut Video-Editing Time: Render video file clips at over 30 percent faster with SSD. You'll be able to edit quickly and move on to your next project in no time.

10. Take it Anywhere: For work that needs to extend beyond home or office walls, SSD exceeds expectations in handling shock, vibration, and temperature extremes. Go anywhere with it.

Are these your top 10?

Oracle optimizes Unbreakable Linux for SSDs. Improves access times by 137%.

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 22 Sep 2010 17:35:24 GMT

This week at its OpenWorld event held in San Francisco, Oracle announced the Unbreakable Enterprise Kernel for Oracle Linux. First and foremost, Oracle Linux is optimized to run Oracle applications software. Buried in the bigger, better, faster claims however is this curious note: Oracle claims that the Unbreakable Enterprise Kernel is 137% faster at accessing files on SSDs than Red Hat Compatible Kernel. This is an example of apps-driven hardware optimization, with a bias towards SSDs. Oracle’s press release doesn’t explain why its Unbreakable Enterprise Kernel is faster, but it’s not hard to guess. OS coders must make assumptions about the underlying hardware running their code and assumptions about disk performance certainly fall into that category. SSDs have substantially different I/O characteristics than do HDDs, and knowledge of that performance difference can certainly help in sizing read/write buffers and making similar disk-access decisions when building an OS kernel. According to the press release, Wim Coekaerts, senior vice president of Linux and Virtualization Engineering at Oracle said “Today’s hardware innovations are fast and frequent -- making it very important that the Linux distributions evolve quickly to leverage the latest hardware.” This is clearly a sign of things to come.

Unsurprisingly, the Unbreakable Enterprise Kernel is now the only Linux kernel Oracle recommends for use with Oracle software.

Samsung whacks DDR3 SDRAM with 36nm stick, knocks 30% off the cost. Elpida and Micron also announce shrinks.

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 21 Sep 2010 21:17:53 GMT

Samsung just announced that it is readying 4Q volume production of 2Gbit DDR3 chips using a 36nm process technology, down from the present 46nm. The shrink will cut the cost 30% and should result in a $1 production cost for a 2Gbit device according to Digitimes.com. In related news, Elpida has announced that it’s readying the transition from 63nm to 45nm SDRAM production and Micron announced a shift from 50nm to 42nm. It looks like we’re starting to see the effects of all that capex investment spurred by the surge in SDRAM sales earlier this year. Here come the DRAM price wars...again.

STEC’s ZeusRAM DRAM-based 3.5-inch SSD has 23 microsecond latency, uses Flash for power-fail backup

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 21 Sep 2010 20:21:21 GMT

This week at Oracle OpenWorld, STEC introduced a DRAM-based, Flash-backed, 6Gbps SAS SSD packaged in a 3.5-inch form factor. The ZeusRAM drive uses DRAM as the primary storage mechanism, which drops data latency below 23 microseconds (fast, fast, fast). For data permanence, STEC’s press release says that the DRAM is “fully backed up” by the Flash. Most likely, the drive contains enough energy storage, possibly in the form of ultracapacitors or a battery, to sustain the transfer of all stored data from DRAM to Flash after an imminent power failure is detected. The drive is already sampling.

Mars Reconnaissance Orbiter crashes, reboots for fifth time

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 21 Sep 2010 17:10:18 GMT

On September 15, the Mars Reconnaissance Orbiter (MRO) went into “safe mode” for the fifth time in two years. “Safe mode” is NASA-speak for entry into standby mode following an on-board computer crash and reboot. NASA’s MRO team successfully restarted the MRO’s computer three days later, which is significantly better than the previous such incident in August 2009. Back then, the MRO needed months to wake up. So why is this a memory story? Because the MRO is perhaps the most complex, certainly one of the most distant Flash-based data-acquisition systems yet built. Depending on their orbital positions around the sun, the Earth and Mars can be between 36 and 250 million miles apart. To date according to NASA, the MRO has generated three times more science data than all other deep-space (beyond the orbit of the Earth’s moon) combined. The MRO successfully completed its primary science mission in November 2008, but it continues to observe Mars and to look for possible future landing sites.

The MRO electronics package is based on a 133MHz BAE Systems RAD750 processor, which is itself based on an IBM version of the PowerPC microprocessor. Reportedly, there are about 150 such processors currently serving in space missions so it’s a proven processor for space. The MRO’s CompactPCI single-board computer combines the RAD750 processor with 36Mbytes of rad-hard BAE SRAM, 4Mbytes of EPROM, and a 64Kbyte boot ROM. All on-board memories employ ECC. Further, the MRO has a 20Gbyte Flash memory module, built from more than 700 256Mbit NAND Flash chips. For comparison, one image from the MRO’s HiRISE (High Resolution Imaging Science Experiment) telescopic imager (nominal picture size = 800 Mpixels) requires about 3.5 Gbytes for storage and there are several other instruments on the MRO also collecting data, so 20Gbytes isn’t all that much storage.

It’s not yet clear from NASA’s reports what caused the glitch, but this space-based event dovetails with the extremely interesting talk given by Karl F Strauss of NASA’s Jet Propulsion Lab at last month’s Flash Memory Summit. As Strauss discussed, NAND Flash devices are most susceptible to ion strikes but they have been growing less and less susceptible to such strikes as device features shrink. For a Flash cell, radiation susceptibility is merely a matter of mass--the smaller the amount of oxide insulation in the Flash memory cell, the less the ability of an ion or photon to become trapped at a defect site and induce leakage. Because radiation tolerance is inversely proportional to memory-cell volume, Flash memory’s radiation tolerance has been steeply increasing over the last few years. Consequently, Flash memory is now even more viable as a candidate for data storage on spacecraft than it was when it was designed into the MRO.

Just how close to the end of NAND Flash are we?

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 20 Sep 2010 21:59:09 GMT

One of the surprises that came from the many excellent presentations given at GlobalFoundrries’ Global Technology Conference (GTC) on September 1 at the Santa Clara Convention Center was a down-and-dirty discussion of the limits of current optical lithography by Senior VP of Technology Gregg Bartlett. Currently, we’re using immersion lithography with 193nm light sources to produce features as small as the mid-20nm range. In fact, a big part of the GTC event was GlobalFoundries’ rollout of its 28nm process technology. To get to 20nm, said Bartlett, you need to use double patterning, which splits a mask into two masks--each with half the required resolution--and then you expose the wafer twice for each mask step using the exposure system to offset the two masks by half the bigger resolution. This procedure doubles mask resolution but it also doubles the cost of each mask step. As a result, wafer-exposure costs jump--quite a lot. In fact they nearly double, which is enough to make alternative lithographic approaches such as EUV (extreme-ultraviolet) and multi-E-beam direct-write lithographies start to look economically viable said Bartlett.

So what’s that have to do with NAND Flash? The top NAND Flash manufacturers are already using mid-20nm lithographies for the current generations of Flash devices. To get to the next process step, the next bump in Moore’s Law, it appears that lithography costs are about to make a big jump in the wrong direction. Worse, that jump may well be the end of the line for optical lithography. To make matters even worse, the constant feature shrinkage has now brought inter-transistor electric field up to the point where disturb problems are apparently becoming significant. All of these factors put pressure on the cost of NAND Flash.

These issues consequently hasten the development of alternative NAND Flash cell designs that are more resistant to field-excited disturb problems and they also hasten the search for commercially viable alternatives to nonvolatile NAND Flash memory. Some of the alternatives include PCM, memristors, and MRAM. However, for the immediate future, NAND Flash continues to reign supreme, unchallenged as long as these competing memory-cell technologies continue to elude commercial production.

But do not be fooled. Every memory technology eventually reaches end of life. Otherwise we’d still be using Williams tubes, mercury delay lines, magnetoresistive wire memories, and magnetic cores. When do you think the end will come for NAND Flash?

PhotoFast SSD leverages PCIe x8 to smash past Gbyte/sec SSD transfer-rate barrier

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 20 Sep 2010 17:25:01 GMT

Want a really fast SSD? You’ll need really fast I/O and PhotoFast’s GM-PowerDrive-LSI SSD employs a PCIe x8 interface to deliver peak read/write speeds of 1500/1400 Mbytes/sec. That’s smokin’ fast, well past the Gbyte/sec read/write barrier and way, way faster than anything possible with single SATA and SAS SSDs. The GM-PowerDrive-LSI drive plugs into a PCIe expansion slot and will be offered in capacities of 256Gbytes to 1Tbyte. It employs a 512Mbyte DDR2 800MHz SDRAM cache to speed accesses to the SSD’s Flash storage. MTBF is said to be 1,500,000 hours, achieved through a 15-bit BCH ECC. Just to scream it’s performance capabilities, PhotoFast packages the drive in a distinctive, fire-engine red case that envelops the PCIe card. For more info, click here.

Intel IDF 2010: SemiAccurate spots Intel SSD with 25nm Flash, new proto SandForce Controller

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 20 Sep 2010 16:53:10 GMT

We were told that it’s coming and SemiAccurate snapped a photo of a prototype SSD clearly labeled with Intel’s 25nm Flash chips and an as-yet-undiscussed SandForce SSD controller chip at last week’s Intel Developers Forum in San Francisco (IDF 2010). To see the photo, click here.

Can magic BEANs eventually grow phase-change memory into a commercial reality?

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 20 Sep 2010 16:41:54 GMT

Researchers at Lawrence Berkeley National Laboratory (LBNL) and the University of California Berkeley have made nanoparticle versions of a germanium tin eutectic alloy that can assume the same sort of amorphous and crystalline states that other materials do in prototype phase-change memory (PCM). Because of the nanoparticles’ low thermal mass, the thermally-excited state transitions take only nanoseconds to occur. The researchers have dubbed the nanoparticles “BEANs” for binary eutectic-alloy nanostructures. While they have not yet directly characterized the electronic properties of the crystalline and amorphous BEAN states, related studies suggest that the electrical and optical properties of the two BEAN states will be substantially different and that the differences can be detected and used in a device. However, for now this finding is that of an interesting nanoparticle phenomenon, yet to be fully characterized, like Rice University’s silicon-oxide memristor discussed earlier. The LBNL and UC Berkeley teams published their findings in the journal NanoLetters and titled “Embedded Binary Eutectic Alloy Nanostructures: A New Class of Phase Change Materials.”

Intel Fellow Speaks SSD Truth at IDF: SSDs “may never” compete with HDDs on cost/Gbyte

denali_mktg@cadence.com (Denali Software, Inc.) — Fri, 17 Sep 2010 17:12:51 GMT

TechRadar.com reports that Intel Fellow Knut S. Grimsrud said SSDs “may never” compete with HDDs on a cost/Gbyte basis. Grimsrud spoke at this week’s Intel Developers Forum (IDF). He’s Intel’s Technology and Manufacturing Group Director of Storage. He suggested that the time when SSDs become cheaper than HDDs on a cost/Gbyte basis is "quite a way off" and that it "may actually never be the case" that the price crossover happens. Of course, that’s not news to readers of this blog and it’s certainly not news to anyone who has listened to analyst Jim Handy speak at MemCon or at other conferences. Perhaps now that someone at Intel has said it, it can become gospel.

However, that’s not really bad news for SSDs. At some point, said Grimsrud, reasonably priced SSDs may store enough to satisfy most typical PC user needs. When SSDs with capacities of 100 to 200 Gbytes cost as little as $30, suggested Grimsrud, then they may well suffice as the only drive in a laptop, netbook, or low-end PC.

Will SD cards become SSDs for the rest of us?

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 16 Sep 2010 20:10:37 GMT

Last night, I came across this interesting article on the ZDNet site about SD cards possibly replacing SSDs. The article’s timely because of the recent announcement made earlier this month by the SD Association about new standards that will increase I/O speeds in future SD card interfaces (previously covered in this blog here). The new SD card interface standards announced by the SD Association set I/O rates nearing 100 Mbytes/sec for SDHC and SDXC UHS-I cards. At that rate, the SD card I/O speeds approach those of today’s low-end SSDs but we can expect such SD cards to be much less expensive than SSDs built to mimic hard-drive form factors. After all, there’s not much material in an SD card beyond the silicon, the plastic molded package, and some I/O pins. And cost is the major stumbling block for SSD adoption at the moment. However, the ZDNet article made me realize that the real tipping point here might well be the 4.0 SD specification--due out next year--which will boost I/O rates to as 300 Mbytes/sec by adding a second row of pins on the SD card to implement additional I/O parallelism through additional I/O channels. Now we’re talking.

SandForce’s big score: $25M investment round and quad-controller PCIe x4 SSD from OCZ

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 15 Sep 2010 23:46:07 GMT

This is SandForce’s week. First the SSD controller-chip vendor announced $25M worth of D-round investment funding to help it design better, faster controllers. Michael Raam, president and CEO of SandForce, said “This new funding will help us bring our next-generation products to market, expand our customer and partner support infrastructure, and accelerate our core technology development that will extend our market leadership.” Sounds like this may be a response to the joint announcement of cooperation on SSD controller development between Samsung and Seagate made late last month.

Second, PC add-on specialist OCZ introduced the RevoDrive X2 SSD with four SandForce processors and a PCIe x4 interface enabling up to nearly 1 Terabyte of NAND Flash storage capacity, more than 730 Mbytes/sec sequential read and/or write performance, and more than 120,000 random write IOPS (4KB block transfer size). This drive’s performance further emphasizes the advantages of employing a PCIe interface for SSDs. The product was introduced and demonstrated at this week's Intel Developers Forum in San Francisco.

A good week by anyone’s measure.

What’s the best SSD for less than $150? Techspot publishes budget SSD roundup.

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 14 Sep 2010 20:40:03 GMT

A year ago, Techspot.com tested and reviewed SSDs and the least expensive drive it worked with at the time cost $270. This year, Techspot has limited its testing to SSDs costing $150 or less. What a difference a year has made. These drives aren’t big--in the 32- to 40-Gbyte capacity range. The competitors tested include the 40-Gbyte OCZ Agility 2 ($135), the 40-Gbyte OCZ Vertex 2 ($124), the 64-Gbyte OCZ Onyx ($130), the 32-Gbyte OCZ Onyx ($85), the 32-Gbyte ADATA S596 Turbo ($83), the 40-Gbyte Intel X25-V ($100), and the 64-Gbyte Kingston SNV425-S2 ($125). In addition to these “low-cost” SSDs, Techspot tested Seagate’s 500-Gbyte Momentus XT hybrid SSD/HDD ($135). As you can see, at the low end there’s a roughly 10x cost/Gbyte difference between SSDs and HDDs at the retail level, even for Seagate’s hybrid drive.

Techspot points out that an end user might want to use one of these drives to boot an OS or an application set to speed work flow. So how did all of these drives fare? See the full Techspot article: http://j.mp/9VQQqP

SanDisk and NDS collaborate to add features and video on demand to set-top boxes through low-cost SSD

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 14 Sep 2010 20:16:34 GMT

NAND Flash vendor SanDisk and set-top box software vendor NDS Group Ltd are collaborating to bring a low-cost means of converting existing set-top box designs into DVRs (digital video recorders) with features such as live pause and video on demand. The hardware vehicle will be SanDisk’s P4 SSDs, which are available in SATA, PATA, and BGA interfaces and it appears to be the SATA interface that’s involved here. The drives need only be small--4, 8, or 16 Gbytes--which is much smaller and therefore much less expensive than what’s now offered with conventional SSDs packaged as 2.5-inch or even 1.8-inch drives. The SSDs will be pre-loaded with NDS’ software called NDS MediaHighway to ease integration into the set-top box.

More here: http://j.mp/ddSPXo

Late Event Notice: The Makers of the Microchip: Creating the Planar Integrated Circuit, Establishing Silicon Valley

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 13 Sep 2010 23:45:53 GMT

You still have two weeks to sign up for an extremely interesting lecture titled “The Makers of the Microchip: Creating the Planar Integrated Circuit, Establishing Silicon Valley” to be presented in Santa Clara at 6 pm on September 28, 2010. The event is sponsored by the Santa Clara chapters of the IEEE Electron Devices Society and the IEEE Computer Society and will be held at National Semiconductor’s Building E Auditorium, 2900 Semiconductor Dr in Santa Clara, California. The high-powered presenters are David C. Brock Senior, Research Fellow, Center for Contemporary History and Policy, Chemical Heritage Foundation and Christophe Lecuyer, Principal Economic Analyst, Office of the President of the University of California.

Now this is a memory blog and, strictly speaking, this isn’t a memory event. However, without the development of the planar IC, we’d all still be using mercury delay lines and memory-core planes woven by Hong Kong tailors to store our bits, so this is truly an important piece of semiconductor history and highly relevant to all things to do with semiconductor memory. The talk presents an overview of the presenters’ new book from MIT Press titled “Makers of the Microchip,” which documents the early years of Fairchild Semiconductor and examines the technological, business, and social dynamics behind the pioneering semiconductor company’s innovative silicon products. The book is based on a collection of documents including the Fairchild Semiconductor's first prospectus; ideas, sketches, and plans for the company's products; and a detailed notebook kept by Fairchild co-founder Jay Last.

The event is free, but you need to sign up here: http://sscsept282010.eventbrite.com/

IEEE Spectrum article provides more insight into HP/Hynix memristor pact

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 13 Sep 2010 20:34:47 GMT

Despite some obvious technical flaws (DRAM cost/bit is not 10x less than NAND Flash! The article means to invoke the cost of hard-disk storage, not DRAM.), this article in IEEE Spectrum provides some additional insights into the recent pact between HP and Hynix to commercialize HP Labs’ memristor developments. Key takeaways:

“Hynix says it is looking to HP’s architecture to form the basis of its next-generation memory strategy.”

Hynix seeks to eventually replace both flash and DRAM with the new [memristor] device.

The goal is to produce devices with 2x the bit density of NAND Flash by 2013.

Pliant trades off firmware complexity against MLC NAND Flash capacity in enterprise SSDs

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 09 Sep 2010 17:06:04 GMT

The multiplicative storage capacity of MLC (multi-level cell) NAND Flash is a siren song to SSD manufacturers but the added storage has a price in terms of access speed and, perhaps more important, data reliability. When you’re storing two or more bits in a NAND Flash cell, there will inevitably be more data errors--which may sound like a really bad thing but it’s not if you have the right perspective. The HDD industry has had the right perspective for decades. Hard-drive engineers know they will be working with imperfect storage media and they have installed the necessary error-management technologies to turn faulty storage into perfect storage. Solid-state-drive engineers are only now really coming to grips with the same situation. After having gone through the designs of the first few generations, SSD design teams are now implementing more complex error-management and wear-leveling algorithms and running them on faster embedded processors to compensate for the new issues cropping up with the use of MLC and TLC (three-level cell) NAND Flash.

Case in point: Pliant Technology, which has just introduced a line of enterprise SSDs with SAS interfaces based on MLC NAND Flash. Pliant based its new new Lightning LB 200M (200Mbytes) and Lightning LB 400M (400Mbytes) enterprise flash drives on MLC NAND Flash memory devices coupled with a new controller design and software that can meet data center requirements for storage capacity and integrity, per an article in Computerworld, written by Lucas Mearian.

However, faster processors and better algorithms cannot compensate for the speed loss when switching from SLC (single-level cell) NAND Flash memory to MLC devices. Pliant’s new 2.5-inch LB-series SSDs can achieve up to 10,000 IOPS, but that’s compared to 35,000 IOPS for the company’s SLC-based LS-series SSDs. But the LS series is currently limited to 150Gbytes in the 2.5-inch format compared to the 400Mbyte maximum capacity of the LB series of 2.5-inch SSDs.

Pliant Technology press release here.

Samsung sees continuing strong demand for NAND Flash

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 09 Sep 2010 16:30:19 GMT

Yesterday, I wrote that Samsung was sending caution messages about DRAM demand based on an expected softening of PC sales. Today, Electronics Weekly's David Manners reports the other half of that story. In the same press conference where he cautioned about DRAM demand, Samsung’s president Oh-Hyun Kwon reportedly stated “Strong demand for chips in tablets and smartphones will offset weakness in the PC market.” He was speaking about NAND Flash demand in these smaller devices shoring up memory demand but small mobile devices tend to use far less DRAM than PCs and far more NAND Flash memory.

Is the latest DRAM bobsled run already coming to an end? Samsung and Hynix say “Maybe”

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 08 Sep 2010 18:13:50 GMT

The semiconductor business has been cyclic ever since it came into existence half a century ago. It seems as though someone at each cycle declares that the business has now learned its lesson and that it will no longer be cyclic. Memory analyst Jim Cantore refuted that meme at the recent MemCon 2010, held in Santa Clara, California. Like all businesses with extremely large capital expenditures, said Cantore, it’s not possible to align the expenditures for new fabs and equipment with the component market ups and downs due to the time lag associated with building and facilitating fabs. The semiconductor memory markets have been on a joyride of late, bringing happy times (and profitability) to DRAM and Flash manufacturers and triggering a new wave of capital expenditures, building capacity for the future. We all know what comes next, even if we hope it won’t. Now, Samsung and Hynix are warning that DRAMs may soon be in oversupply, resulting in falling ASPs.

"If the PC market continues to slow, we may see a kind of oversupply in Q4 or Q1," said Kwon Oh-hyun, head of Samsung's chip business, at a media conference at its annual mobile solutions forum in Taipei.

Hynix has reportedly given the same sort of warning.

However, there’s not much news here, really. We know the DRAM and Flash markets rise and fall cyclically, largely based on PC sales. At the same time, new gadgets such as smartphones and the imminent release of products to compete with the Apple iPad provide new high-volume channels for selling DRAM and NAND Flash memory. With so many overlapping sales cycles, it’s not possible to predict the future with any certainty, other than to say there are certain to be ebbs and flows. But you knew that already, didn’t you?

Icy Dock internal multi-drive bay crams four 2.5-inch drives (SATA or SAS) into 5.25-inch slot (with video)

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 08 Sep 2010 17:21:24 GMT

OK, so this blog entry isn’t about memory so much as it’s about a cool ancillary product that you’ll want to look at--the Icy Dock MB994SP-4S 4 in 1 SAS / SATA Hot Swap Backplane RAID cage. This neat little example of metal bending allows you to cram four 2.5-inch drives (SSDs, for example) into one 5.25-inch drive bay. The dock comes with four little metal carriers for 2.5-inch drives and each drive bolts into a carrier using the drive’s four bottom-screw holes. The carriers then snap into the bay. Side-to-side space is at a premium, so Icy Dock devised carriers with zero side clearance; The carriers are no wider than the 2.5-inch drive.

You’ll find two power connectors, four drive data connectors (SAS or SATA), and two fans on the bay’s back panel. The bay senses when drives are present and only switches on a fan if it has one or two drives to cool. Because the bay brings each of the four drives’ data connectors out separately (no multiplexing) you can use the cage as a RAID bay or simply to house four independent 2.5-inch drives in an otherwise unused 5.25-inch drive slot. The bay with four drive carriers currently sells for slightly more than $50 at NewEgg.

Here’s a very short video to illustrate the concept.

Super Talent caches Flash memory on USB 3.0 drive with 32 Mbytes of DRAM, performance improves as much as 300%

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 08 Sep 2010 16:09:26 GMT

There’s been plenty of discussion about using NAND Flash memory to cache HDDs and now Super Talent has introduced 32- and 64-Gbyte Flash-based USB 3.0 stick drives that incorporate 32-Mbyte DRAM caches to boost small block random performance by up to 300%. DRAM caching is not particularly new for SATA and SAS SSDs designed to replace HDDs but the Super Talent USB 3.0 Express RAM Cache drive looks like an ordinary USB stick. It has a USB 3.0 interface and is backward compatible with USB 2.0 ports as well. The DRAM cache is needed because the much faster transfer rates possible with the USB 3.0 specification can easily outstrip the read/write speeds of the drive’s internal Flash memory. Quoting an email from Super Talent:

“Sequential read and write speeds only show how a drive will perform when copying large files. In 'real world' applications, we are often reading and writing 100's of smaller files and in some cases even booting to the drive. In these instances traditional flash deigns show their weakness and a caching system can dramatically improve performance. For example, say you wanted to copy 40 MP3 files to your flash drive. By adding a caching system, the Express RAM Cache drive can now write these same files 260% faster; instead of taking 13 seconds, this transfer now takes less than 5 seconds. As the file size decreases and the file count increase, this time savings becomes even more apparent.”

The 32- and 64-Gbyte versions of the Super Talent USB 3.0 Express RAM Cache list for $129 and $209 respectively.

SD Association adds pins to SD card format to boost transfer rates to 300 Mbytes/sec

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 07 Sep 2010 21:25:55 GMT

Hot on the heels of the rollout of high-speed SDHC and SDXC UHS-I cards that approach 100 Mbytes/sec (see previous blog entry), the SD Association has unveiled plans to add more pins to the physical SD package to boost read/write transfer rates into the hundreds of Mbytes/sec. The UHS-I spec currently has a maximum transfer rate of 104 Mbytes/sec. The new 4.0 SD specification, due out early next year, adds a second row of pins behind the first row to boost bandwidth to as much as 300 Mbytes/sec through I/O parallelism. Cards with the second row of pins will be backwards compatible with the existing single-row cards. (Press release here.)

Toshiba to ship 32-Gbyte SDHC UHS-I cards with 95/80-Mbytes/sec read/write speeds

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 07 Sep 2010 20:58:36 GMT

If you’re a rabid fan of Canon dSLRs, you already know of the many controversial decisions made by Canon when it recently introduced the Canon 60D camera, the latest in a long line of xxD digital SLR cameras. Among the changes, Canon eliminated the use of Compact Flash (CF) cards in the 60D and added an SD card slot instead. This decision (among others) caused quite a cry to arise from Canon aficionados, who feel that the slower memory bandwidth of SD cards will impair the Canon 60D’s ability to quickly drain a filled image buffer while shooting bursts of RAW images. The Canon 60D will be available at the end of September and Toshiba will be fixing this particular problem for the 60D by November, when the company plans to initiate volume production and ship 32-Gbyte SDHC UHS-I cards that conform to the SD Memory Card Standard Ver. 3.0 (SD 3.0), UHS104. These SDHC UHS-I cards feature 95/80-Mbytes/sec maximum read/write transfer rates, which put them very close to or equal to the maximum transfer rates of high-performance CF cards. Toshiba plans to ship 32-Gbyte SDHC UHS-I cards in November and 8- and 16-Gbyte cards in December. Toshiba’s also plans to ship microSDHC UHS-I cards in November, which comply with SD 3.0, UHS50, with maximum read/write speeds of 40/20 Mbytes/sec. (Press release here.)

Rice U’s silicon-oxide memristor more phenomenon than device, for now

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 07 Sep 2010 18:20:27 GMT

Last Friday, I wrote about a memristor development out of Jim Tour’s nano research group at Rice University. The development involves the observation of nonvolatile memristance-like behavior in silicon oxide, rather than the titanium dioxide employed by HP’s memristor. Silicon oxide is a well-understood substance used in every silicon-based IC device now made. Presently, it’s used strictly for insulation, so seeing memristance behavior in the material is revolutionary and exciting. The information for Friday’s blog entry came from a press release about the publication of a paper on the observed phenomena in the most recent American Chemical Society’s Nano Letters. Over the weekend, I obtained a copy of the article (thanks to the King Library, jointly run by San Jose State University and the city of San Jose) to delve further into the announcement. What I learned is that the paper covers the early observation of an interesting phenomenon. We’re pretty far from a working memristor memory chip made from silicon dioxide.

The paper published in ACS Nano Letters describes a test chip consisting of 200 50-micon circular pillars. Polysilicon electrodes sandwiching a 40nm-thick silicon oxide layer comprise each pillar. The 50-micron diameter allows each pillar to be probed with a microprobe for experiments. There is no active circuitry on the test chip. The paper’s description of silicon oxide sort of reset my basic understanding of the material, which was based on high-school and university chemistry courses from too long ago. I had always envisioned silicon dioxide as having two oxygen atoms bound to each silicon atom. My mistake. It’s important not to have this image of silicon dioxide when thinking about the silicon oxide in this experiment. Think more of a silicon lattice infused with oxygen atoms. Mobile oxygen atoms. The proper chemical formula is SiOx where x ranges from 1.9 to 2. Think of free-range oxygen.

An electric current can drive the free-range oxygen out of a localized region of silicon leaving pure silicon nanocrystals that conduct substantially better than the surrounding silicon oxide. With enough current applied for a long enough time, a chain of conductive nanocrystals forms along the current path and creates a relatively high conductivity (relatively low-resistance) silicon filament between the two electrodes. The paper proposes electron tunneling conduction as the mechanism for creating the initial current that forms the silicon nanocrystals.

Driving oxygen out of a material is called reduction (the opposite of oxidation) and the authors of the paper have included electron microscope images showing the filament of silicon nanocrystals formed by the electrically driven reduction process. Further experiments indicate that the reduction is a surface phenomenon and only occurs on the annular surface of the silicon oxide disk within the pillar sandwich in this experiment. Applying an oxygen atmosphere appears to prevent the formation of silicon nanocrystals, which will form under the same electrical conditions in a nitrogen atmosphere or in a vacuum. Together, the electron microscopy photos and the interfering nature of free atmospheric oxygen support the premise that the observed phenomenon is due to an electrically induced reduction reaction. The paper’s authors call this reduction process the “set” mode because it sets the “device” into the relatively low-resistance state. The reset mode, which places the device back into a high-impedance state, is “more likely” to be induced by electrically driven thermal heating, according to the theory published in the paper. The set mode requires 100nsec, 6-8V pulses and the reset mode requires 13V, 50nsec pulses. There’s a repeatable, 5-orders-of-magnitude difference in resistance between the set and reset states of the device--something that can easily be sensed on a chip.

So what we have here is the initial observation of a very interesting nanoscale phenomena based on silicon that’s still far removed from even a prototype device. There’s still a lot of engineering to be done here before we even start to work towards a commercial product based on this phenomenon.

Update on Viking’s SATADIMM SSD--no cable needed, Sandforce SSD controller

denali_mktg@cadence.com (Denali Software, Inc.) — Fri, 03 Sep 2010 20:47:06 GMT

Previously, I wrote about Viking’s SATADIMM, an SSD built into a standard DDR DIMM (see “SSD Form Factors: Viking Modular Solutions talk at Flash Memory Summit explodes the possibilities”). Michael Bloebaum, owner of a company in the Netherlands named SSD Distribution, “announced” Viking’s SATADIMM in LinkedIn’s Solid State Disk Innovator’s group and prompted some good discussion. Gene Patino, VP of High Performance Products at Justyn Tyme Solutions in Orange County, California commented that the SATADIMM merely uses the DIMM socket for a convenient and omnipresent power outlet and that the SSD’s SATA interface is on a separate connector, accessed via a SATA cable. Then Steve Garceau, a Senior Product Manager at Viking Modular Solutions commented that the SATADIMM’s SATA interface is also easily accessed through the DIMM connector; that it is relatively easy and cost-effective to design a motherboard with a DIMM socket that accepts either a standard DDR SDRAM DIMM or a Viking Modular Solutions’ SATADIMM; and that the motherboard BIOS can be configured to automatically detect the type of DIMM occupying the socket so that the system can be appropriately configured. Have your cake and eat it too.

Also in this discussion, both Bloebaum and Patino stated that the Viking SATADIMM employs a Sandforce SSD controller.

Rice University reports that silicon oxide also good for memristors

denali_mktg@cadence.com (Denali Software, Inc.) — Fri, 03 Sep 2010 18:14:22 GMT

Hot on the heels of the announcement earlier this week that Hynix is now an active partner in commercializing HP’s titanium-dioxide memristors, a research team at Rice University in Houston, Texas has announced that it has discovered silicon oxide structures that also exhibit memristance. The Rice team, including nanomaterials specialist Jim Tour, and a design house named PrivaTran in Austin, Texas were experimenting with a graphene-based crossbar design, looking for memristance behavior in graphene, when they observed the sought behavior in the silicon-oxide dielectric spacers placed on the graphene chip. The resulting silicon-oxide memristor exhibits nonvolatile storage, a high on/off resistance ratio (>10^5), sub-100-nsec switching time, and a write/erase endurance of 10^4 cycles. The team has published their findings in the August 31, 2010 ACS (American Chemical Society) Nanoletters Journal (http://pubs.acs.org/doi/abs/10.1021/nl102255r).

(As reported in EETimes -- http://www.eetimes.com/electronics-news/4207276/Rice-s-silicon-memristor-aims-to-beat-HP -- and The New York Times -- http://www.memristor.org/news/467/scaling-memory-rice-university-hp-labs-privatran-phase-change-memory)

The 6-minute video guide to memristors (must-see video)

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 02 Sep 2010 21:42:12 GMT

With the August 31 announcement that Hynix is now working with HP to bring the semi-mythical memristor to market in commercial devices, I went searching for a good explanation of how HP’s memristors are made and how they work. It turns out that they are anatomically simple and relatively easy to understand, if you have the right teacher. HP’s R. Stanley Williams is the right teacher, for me at least, and he made a 6-minute video with the IEEE back in 2008 detailing pretty much all you need to know if you want to understand memristance and how you make HP-style memristors. Here’s the video: