SoC and IP

UCIe and Automotive Electronics: Pioneering the Chiplet Revolution

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 30 Apr 2024 05:34:00 GMT

The automotive industry stands at the brink of a profound transformation fueled by the relentless march of technological innovation. Gone are the days of the traditional, one-size-fits-all system-on-chip (SoC) design framework. Today, we are witnessi...(read more)

Celebrating World Intellectual Property Day

denali_mktg@cadence.com (Denali Software, Inc.) — Fri, 26 Apr 2024 20:36:00 GMT

LEGO^® is the world’s most famous toy brand. The experience of playing with these toys has endured over the years because of the innumerable possibilities they allow us: from simple textbook models to wherever our imagination might take us. We have always been driven by a motivation to reuse modular components in all facets of our lives that enable us to build things better and faster while reducing complexity, allowing us to focus our innovation on areas that matter most to us.

In semiconductor design, cost and complexity are closely intertwined.

Figure 1: Advanced node design cost [IBS Global Semiconductor Service Report Design Activities and Strategic Implications, July 2018]

Design and verification costs, as well as the length of design cycles, have risen dramatically as process nodes have advanced. IP allows for design scalability and product development schedules to be feasible in this situation.

From the simplest building blocks like GPIOs to the most advanced high-speed interfaces, IP subsystems are the lifeblood of the chipmaking ecosystem. A key enabler for IP has been the collaboration between industry and academia in the creation of standards and protocols for interfaces. IEEE, JEDEC, PCI-SIG, the CXL Consortium, and the UCIe Consortium, to name a few, drive some of the key definitions and compliance specifications and ensure the interoperability of interface IP.

In the processing world, Arm^® leads the way with its wide offering of CPUs and interconnects. Other alternate providers are making their entry as well. Specialized accelerators for DSP, such as Cadence’s Tensilica and Neo AI accelerator IP, aim to accelerate these portions of SoC,s too.

Verification IP complements the design IP. Without a comprehensive verification and validation environment, no design can succeed. The investment to build this capability in-house is prohibitive even for the most advanced companies today.

Figure 2: IP Accelerates Customer Designs

The IP spectrum covers a wide gamut to meet all needs. Like the most common 2x1 Lego brick to the rarest 14-karat gold Bionicle Lego piece, IP ranges from the simplest RTL block of code to the most complex custom physical designs. On this World Intellectual Property Day, we take a moment to celebrate all those who make this ecosystem possible in order to bring us the wonderful designs that make technology a reality in our day-to-day lives!

Intel and Cadence Partner to Build Out the Foundry Ecosystem in America

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 28 Mar 2024 16:00:00 GMT

As a result of the largest public-private investment ever made in the U.S. semiconductor industry, Intel Foundry has announced plans to expand semiconductor facilities in Arizona, Ohio, New Mexico, and Oregon. The investment is aimed at building up a resilient domestic and global supply chain and a world-class foundry business.

Boyd Phelps, SVP and GM, Silicon Solutions Group, Cadence, and Gautam Singampalli, Director of Product Marketing, Cadence, at the demo booth, Intel Ocotillo Campus, Chandler, AZ

Cadence was invited to showcase its advanced solutions in Intel technology at their Arizona facility. The Cadence team demonstrated the Subsystem Test Chip for PCIe 5.0/CXL 2.0 built using Intel Foundry technology, seamlessly interoperating with a commercially available off-the-shelf Intel Alder Lake client platform (desktop PC).

Pat Gelsinger, CEO of Intel, visiting the Cadence demo booth

Cadence demonstrated silicon success in a live working demo at Intel’s inaugural IFS Direct Connect event in San Jose, CA, in February and now at this event at Intel’s Ocotillo Campus in Chandler, AZ.

Among the VIPs who witnessed the demo was Pat Gelsinger, Intel CEO, to whom Cadence Marketing team highlighted the capabilities of our test chip implementation on the Intel process technology. In his remarks to the audience, Pat said,

“We hope to be manufacturing the most advanced AI chips for many of the major semiconductor companies in America, taking advantage of the R&D that is done uniquely in America. And that’s why today is such a thrilling moment.”

Stuart Pann, Senior Vice President and General Manager, Intel Foundry, took this opportunity to show the live Cadence demo to SoftBank Group Corp. founder Masayoshi Son

Rich Uhlig, Intel Senior Fellow and Director of Intel Labs, stopped by to check out the big open-eye diagrams of live PCIe 5.0, 32Gbps data traffic flowing between the Cadence subsystem and the Intel Alder Lake platform.

Lip-Bu Tan, Intel Board Member and former Executive Chair and CEO of Cadence

Intel Board Member and former Cadence Executive Chair and CEO Lip-Bu Tan also had many thoughtful questions about the Cadence Subsystem Test Chip for PCIe 5.0/CXL 2.0 built using Intel Foundry technology. He was pleased to see the Intel Platform change PCIe rates and use the Cadence GUI to monitor and plot real-time eye diagrams of live traffic after each rate change up to 32Gbps.

U.S. President Joe Biden addressed the select group of VIPs, government officials, union leaders, and key Intel partners at the Intel Ocotillo Fab Construction Zone

President Joe Biden announced the historic news about the U.S. government’s partnership with Intel to build world-class, commercially viable leadership in technology and the plans to add to these capabilities and the additional requirements to defense and intelligence, thereby affirming Pat’s statement about reaching the “end of the beginning of our journey to rebuild semiconductors in America.” In his remarks to the audience, the president said:

We're just getting started. The CHIPS and Science Act has led the partnership with companies investing billions and billions of dollars across the country bringing semiconductor manufacturing back to America. …

We are going to once again begin to make the most sophisticated, advanced, and powerful leading-edge chips. It blows my mind that each chip has trillions of tiny features the width of a strand of human DNA. 40,000 times thinner than a single human hair. They require manufacturing precision down to the size of a single atom. The process is enormous. Requires enormous amounts of information and lightning speed they'll produce. They're critical to emerging technologies. They're going to power the future economy like artificial intelligence, quantum computing, 6G communications, and make everything faster, lighter, smaller, and more reliable. …

This is going to transform the country in a way we don't even understand yet.

Learn more about Cadence's IP products offered by the Silicon Solutions Group.

Revolution on the Road: How Cadence is Driving the Future of Automotive Design!

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 06 Mar 2024 05:00:00 GMT

The automotive industry is at a crucial inflection point, pivoting from traditional vehicles to intricately designed marvels of technology. This metamorphosis is evident not only in the vehicles on the road but in the fabric of their functionality—the silicon at their heart. For instance, cars these days do a lot more than drive—they think, react, and adapt. This transformation has led to a burgeoning relationship between automotive and semiconductors, turbocharging the semiconductor market's growth.

However, navigating through the rapid evolution of the automotive industry—one marked by advancements in autonomy, connectivity, and electrification—engineers and experts face the formidable challenge of transforming vehicle electrical and electronic (E/E) architectures. This is where Cadence Innovative IP and other products come in to make this transformation easy. Cadence offers a vast array of innovative IPs and tools; the wide product range covers a variety of applications, from infotainment systems to functional safety and system analysis.

This post is an excerpt from Robert Schweiger’s talk at the CadenceLive Europe 2023. It discusses the changing trends and impacts of transformation on automotive SoC and system design and highlights Cadence pivotal role as an enabler of this evolution

Recent Trends in the Automotive Industry

The semiconductor industry, as forecasted in the August 2023 IBS Semiconductor Industry Outlook, is poised for substantial growth in the automotive sector, with an anticipated increase of 12.98% in 2024. This surge is chiefly attributed to the rapid advancements in vehicle electrification, autonomy, and software-driven innovations. Leading semiconductor corporations alongside agile startups are at the forefront of this transformation, particularly in sensor technology and artificial intelligence. These pioneering efforts are resulting in revolutionary enhancements across the industry. As vehicles evolve from incorporating advanced driver-assistance systems (ADAS) to achieve full autonomy, the progression is meeting and exceeding consumer expectations, marking significant milestones in in-depth perception and intelligent driving technologies. With the evolving automotive industry, the below trends are pretty much straightforward:

Drive toward Advanced semiconductor nodes
- 3D-IC design, Chiplets
- 5nm, 3nm gate-all-around (GAA)
Changing Architectural Paradigms in Automotive Design

Advanced Semiconductor Nodes: The New Vanguards in Automotive Chips

Today's automobiles have evolved far beyond their original purpose of simply transporting individuals. They have become luxurious havens of comfort and safety, equipped with sophisticated features. ADAS, comprehensive onboard entertainment systems, and seamless connectivity options are standard expectations in new vehicles. These features are not just about opulence—they've redefined driving or riding in a car. SoCs must deliver multifunctionality and reliable performance to accommodate these complex requirements, even under the most challenging conditions. Cutting-edge processing technologies like the 5nm—and fabrication processes are at the forefront, paving the way for SoCs with formidable computing capabilities and superior energy efficiency. This powerful combination is essential for powering the sophisticated operation of modern vehicle amenities.

Changing Architectural Paradigms in Automotive Design

Gone are the days when vehicles operated on mechanical prowess alone. The heritage of domain-based architectures, where electronic control units (ECUs) were tailored to specific functionalities like powertrain controls or infotainment systems, is being outpaced by today’s sophisticated and zone-based architectures. The heart of these modern vehicles lies in semiconductors—generating power, managing systems, and thriving on data. The complexity of modern vehicles and the level of automation involved has made it necessary to move from traditional domain-based architectures to zonal architectures.

There are many reasons for this transition, such as:

Scalability Gridlocks
Communication Conundrums
Software Update Struggles

The shift towards electrification and hybridization is as much another primary reason for change in architecture.

Impact on Semiconductor Design

Semiconductor design in the automotive industry has always been wrought with unique challenges. The current epoch is no exception, as the transition to SoC architecture calls for reevaluating design philosophies and methodologies. The transition to a zonal architecture presents myriad challenges, chief among them being the need for a robust high-bandwidth network connecting these autonomous zones. Existing vehicle networks were not designed with such requirements, necessitating a ground-up redesign. And need not mention the reduced time to market!!

Engineers increasingly employ innovative design techniques such as chiplet integration and 3D layouts to pack more functionality within a limited space while ensuring the chip's design is amenable to mass production. Such advancements are increasing concerns related to power consumption, thermal management, electromagnetic interference (EMI), cybersecurity, and functional safety are overarching considerations that must be considered in pursuit of the ideal system.

Challenges: Zone-based architectures

How Cadence Tools are paving the way to this transformation

Cadence has emerged as a crucial player in advanced automotive technologies, providing a comprehensive suite of solutions for intricate systems analysis that addresses today's increased complexity. Its portfolio ranges from IP to system-wide solutions, including verification, emulation, thermal, electrical, and fluid dynamics performance evaluations. These tools validate and predict system performance under various conditions, enhancing vehicle integrity and accelerating development timelines.

Cadence's innovation is vital to automotive design, supplying essential IP for creating sophisticated electrical/electronic architectures that pave the way for autonomous driving. Focusing on both hardware and software solutions, Cadence Tensilica DSPs and Neural Processing Units (NPUs) lead in processing power for automotive applications, further enhanced by the configurable and extensible Xtensa Processor platform, which integrates AI and machine learning with ease.

Cadence offers a myriad of solutions for automotive, such as ADAS/AD, Infotainment, ADAS, simulation VIP, Verification, emulation, system design, etc.

ADAS/AD

Cadence offers scalable computing solutions powered by AI engines and DSPs for ADAS and autonomous driving. For autonomous vehicles, designers use high-performance computing fueled by zonal architecture, sensors, and advanced SoCs where radar, Lidar and camera play a significant role. Cadence extends its Tensilica DSPs and AI engines for such applications, proffering a scalable solution ranging from 0.25 to hundreds of TOPS, ideal for sophisticated computing demands. Their multi-core AI platforms epitomize efficiency, tailored for high-performance computational tasks.

In-Cabin Experience/ Infotainment

In-cabin experiences are evolving significantly, focusing on heightened connectivity and advanced infotainment systems. Cadence NeuroWeave SDK bolsters scalable hardware for AI applications, addressing needs from in-cabin monitoring to speech recognition and object classification. Cadence's automotive Ethernet IP solutions are at the forefront, driving the development of high-performance, reduced-latency vehicular networks.

Alongside state-of-the-art audio and video DSPs, they ensure that in-car experiences transcend mere function to become truly immersive. We offer processor and interface IP (Controllers and PHYs) support at advanced nodes (down to 5nm). All these solutions meet ISO26262 and support AEC-Q100 temp ranges. Further, the recent acquisition of PHY IP from Rambus has strengthened the SerDes and memory interface support.

Simulation Verification IP (VIP) for Automotive

Our comprehensive Verification IPs (VIPs) suite is designed to meet the stringent demands of modern Ethernet and interface standards. For Ethernet Time-Sensitive Networking (TSN), we offer a mature, feature-rich compliance verification solution that includes a full protocol stack, bus functional models (BFM), and integrated protocol checkers with coverage capabilities, ensuring seamless integration into test benches at both IP and system levels. Our VIP for Ethernet Base-T1 (PHY) for physical layer testing supports all Base-T1 speeds, including 10Mbps, 100Mbps, and 1Gbps, ensuring thorough and flexible testing scenarios. In sensor application interfaces, our VIP for MIPI A-PHY offers robust support for CSI2 and I2C, complying with MIPI A-PHY v1.0 and v1.1 specifications. Our PCI Express Verification IP is unmatched for high-speed data transfer, supporting PCIe 3.0, 4.0, and 5.0 and catering to leading-edge IP and SoC verification requirements.

MIPI A-PHY: Sensor Simulation Verification: A-PHY with CSI2 and I2C VIPs

Finally, our VIP extends to supporting all CAN standards, ensuring comprehensive verification coverage for CAN, CAN-FD, and CAN-XL specifications. Our VIP lineup is purpose-built to ensure that your products meet the rigorous standards of performance and compliance demanded by these advanced technologies.

Chiplets and Automotives

The global chip market is rapidly growing due to increased demand from the automotive industry, spurred by the rise of advanced driver-assistance systems (ADAS), electric vehicles (EVs), and connected cars. These applications require superior data processing and sensor capabilities, driving innovations such as chiplets, which may become the aggregator of IP into systems and subsystems. Chiplets are a promising alternative to monolithic SoCs that offer lower costs, higher performance, and greater flexibility. Chiplets are also a key enabler of heterogeneous and modular SoC design, which can accelerate innovation and adaptation in the electronic industry.

Cadence has emerged as a comprehensive solutions provider, addressing these challenges with tools such as the Integrity 3D-IC Platform, which unifies disparate design tools, and the Allegro X Design Platform, facilitating PCB design for laminate-based packages. This shows a clear path forward in the automotive industry's evolution, highlighting the critical role of high-performance chips and chiplets in enabling cutting-edge automotive technologies. Moving forward, the flexibility offered by chiplets will likely be vital in meeting the dynamic needs of the market, promising an exciting future for automotive electronics.

As a leader in chiplet-based SoC design, Cadence demonstrated at the recent Chiplet Summit 2024 in San Jose, for the first time, a test chip that includes seven chiplets, each with two UCIe PHY blocks.
We showcased an industry-first eye-diagram measurement of a die-to-die interconnect with speeds of up to 16GT/s on an oscilloscope. This successful implementation of UCIe IP on first-pass silicon is a milestone in die-to-die connectivity!

Learn More

Cadence Sets the Gold Standard for UCIe Connectivity at Chiplet Summit '24

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 28 Feb 2024 21:46:00 GMT

Cadence Demonstrated first silicon in UCIe during Chiplet Summit 2024. The demo showed successful operation at 5mm, 15mm, and 25mm channel lengths, at all data rates. The signals were brought out to an oscilloscope and showed wide open eyes at all data rates. FPGA prototype demonstrated how it can be used by customers to build their stack, significantly reducing design cycle time.(read more)

UCIe Interoperability Between Intel and Cadence

denali_mktg@cadence.com (Denali Software, Inc.) — Tue, 07 Nov 2023 21:30:00 GMT

Intel and Cadence are collaborating on an initiative to demonstrate interoperability between Intel’s UCIe IP and Cadence’s UCIe IP.

UCIe is the latest emerging open specification defining the interconnect between two die links in a system in package (SiP). UCIe is expected to enable power-efficient and low-latency chiplet solutions as heterogeneous disaggregation of SoCs becomes mainstream to overcome the challenges of Moore’s Law. The UCIe 1.0 standard, dated February 24, 2022, first became available in March 2022. A newly updated UCIe 1.1 specification was recently released and announced on August 8, 2023.

Emerging new standards often present unique challenges and limited opportunities for interoperability. Intel and Cadence have collaborated on simulation interop initiatives for a number of years and previously demonstrated CXL and PCIe-IDE interoperability as these new standards emerged. Intel and Cadence are now working together to demonstrate UCIe interoperability of Intel’s UCIe IP and Cadence’s latest UCIe IP solutions. The first step towards this collaboration is a demonstration of pre-silicon RTL co-simulation interoperability.

The lack of a platform for interoperability testing provides a challenge on how to show that an IP was developed according to the UCIe specification. This is especially critical as the standard is evolving from Revision 1.0 in 2022 to Revision 1.1 in 2023. The UCIe simulation discovery process developed by Intel and Cadence was designed to ensure both Intel and Cadence PHYs are functionally interoperable per the UCIe specification and to make the debugging of issues that may arise during the interoperability test easier and more efficient.

The Figure 1 diagram illustrates the UCIe simulation framework of the RTL interoperability environment between Intel and Cadence.

Figure 1. UCIe simulation framework

The Cadence UCIe advanced package PHY model with x64 lanes was used for pre-silicon verification with Intel’s UCIe-generated vectors. The Cadence UCIe layers consisted of testbench-style bus functional models (BFMs) that responded to incoming requests from Intel UCIe vectors and initiated outbound requests via Verilog tasks. The UCIe sideband was used for initialization, link training, and messaging between the die links. Parameter information, which could include data rate negotiation or link training results with the link partner, was exchanged over the sideband interface.

The link training state machine (LTSM), shown in Figure 2, is defined in the UCIe specification. The link states from RESET to ACTIVE were followed at a high level to step through each state for initialization.

Figure 2. LTSM – From the UCIe Specification, Revision 1.1

During interoperability testing, in addition to verifying the proper operation of the LTSM, we were able to monitor and verify important interoperability steps such as PHY lane check order, ensuring each state is entered and exited successfully. Regression testing and interoperability simulation between the established die links was an opportunity to improve the robustness of both PHYs. It also aimed to validate the designs against various areas of the UCIe specification in order to improve the quality of both products.

The next step is to enable controller simulation interoperability by building on top of the physical layer, similar to the controller interoperability work performed by Intel and Cadence since 2020 for CXL1.1, CXL2.0, and PCIe-IDE. The application layer enhancement with the addition of the controller, FDI interface, and client interfaces will be tested using the RAM model.

In conclusion, as the UCIe specification continues to evolve, there is a drive to set up an open standard ecosystem to enable design IP, verification IP, and testing practices for compliance. To keep up with the rapid pace of the chiplet ecosystem expansion, simulation, and interoperability testing between different sources of UCIe IP is essential. As in the case of Intel and Cadence described above, it helped to quickly and more confidently validate the UCIe design IP, delivering a better product.

To learn more, visit the Cadence UCIe PHY and Controller Design IP page or Contact Us.

More details on UCIe VIP are available on the Cadence Verification IP Portfolio page.

Learn more about the Intel and Cadence Pre-Silicon Simulation Interoperability CXL Case Study.

For more information on UCIe in general, visit the UCI Express website.

Cadence is a Contributing UCIe Consortium Member

denali_mktg@cadence.com (Denali Software, Inc.) — Fri, 03 Nov 2023 05:15:00 GMT

This blog was originally posted on uciexpress.org.

The Cadence member spotlight blog is live and can be found here

Meet UCIe Consortium Member Cadence

By: Sue Hung Fung, Principal Product Marketing Manager, Cadence

Can you share a brief introduction to Cadence?

Cadence (Nasdaq: CDNS) is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

For nine years in a row, Cadence was listed on the Fortune Magazine 100 Best Companies to Work.

What prompted Cadence to join the UCIe Consortium?

Cadence became a contributor-level member at the initial opening of the UCIe Consortium. Prior to joining the Consortium, Cadence demonstrated and proven capability in chiplet IP with their proprietary 40G die-to-die solution. Joining the UCIe Consortium gives Cadence the opportunity to participate in the advancement of the open chiplet ecosystem. Our representative’s expertise, knowledge, and familiarity with chiplets, PCIe, CXL, and streaming protocols allow Cadence to rapidly design and develop UCIe technology. The rapid scaling of silicon-proven functionality and architecture improves customer time to market and reduces developmental risk in the design implementation of UCIe.

What is the importance of a chiplet ecosystem to Cadence?

Cadence enables die-to-die IP designs and solutions. Engagement in the open ecosystem provides a path forward to producing reusable chiplet IP for interoperability with other chiplets. Interoperability in the chiplet ecosystem and provision of a fully integrated PHY and controller UCIe platform solution allows customers to reduce product development time to focus on their own design and custom needs.

Customers can lower their overall portfolio costs and accelerate their product development cycles by reusing chiplet designs already established on their preference of process nodes. By reusing designs on a variety of established process nodes, on-package integration of those designs can be used to lower overall portfolio costs. Cadence’s engineering teams are well equipped to rapidly create a variant of the UCIe PHY and controller aimed at lowering system power, increasing bandwidth and throughput, and reducing overall die-to-die link latency.

How does Cadence contribute/plan to contribute to the Consortium?

Cadence currently engages in the electrical, form factor and compliance, manageability and security, protocol, systems and software, and marketing working groups to help steer and develop the new chiplet open standard. Cadence has a broad portfolio of automotive IP solutions and is currently engaging in the Automotive Working Group. Cadence’s extensive experience and history in the design and development process of die-to-die solutions will efficiently impact UCIe’s future course of action to create a strong infrastructure around these specific Working Group categories within the UCIe standard.

Cadence currently has PHY and controller IP solutions in PCIe and CXL. Cadence’s proprietary chiplet controller solutions already offer streaming, CXS.B, and AXI protocols on chiplet interfaces. Building upon prior experience, the extensive background and expertise in these current IP and chiplet solutions provide a knowledge base to contribute and improve upon within the Consortium.

Can you share some UCIe technology use cases that Cadence is bringing/will bring to the industry? Are there any specific market segments that will benefit most from UCIe?

The automotive segment is a strong focus where Cadence is proud to bring expertise and improvement to the open standard. Cadence has a broad portfolio of automotive controllers and PHY IP solutions. The UCIe Protocol Working Group has addressed mainband data integrity protection as a part of ECN1 in the next UCIe Rev 1.1. By adding CRC and retry for a UCIe streaming controller, automotive applications can lean heavily on CRC as the primary safety mechanism for the mainband data path. In addition to this, Cadence is providing a proprietary proposal to ensure sideband message protection and integrity for automotive safety.

Cadence’s EDA tools for advanced and standard package designs allow customers to sign off with full integration of multi-chiplet design. With top-level planning, 3D place and route, packaging, and thermal analysis, Cadence’s tools provide designers with full capability to improve PPA, increase performance, and close timing.

Do you have any news or updates you want to share regarding your company’s roadmap for UCIe?

Cadence is currently offering UCIe on multiple foundries and nodes and has taped out an advanced-package UCIe solution on 3nm. We are working with multiple customers towards the expansion of UCIe on additional technology process nodes at a variety of foundries and across both standard and advanced package options.

Cadence is also working with multiple customers to focus on automotive applications with UCIe. With a vast track record of automotive products already available, the addition of UCIe to the portfolio will enable customers to scale their products for robust automotive applications in chiplets.

What would you say to a company considering joining UCIe and supporting the chiplet ecosystem?

UCIe is the open standard of the future of interoperable chiplet communication. Die link communication via UCIe’s standard will advance an open ecosystem where chiplets from different vendors can be designed for interoperability. With die sizes reaching their maximum reticle limits, the need for disaggregation of SoCs will drive future-generation designs to move toward chiplet solutions. Smaller die will result in higher manufacturing yields and lower costs. Chiplets will allow flexibility on the process nodes of choice (heterogeneous platforms), where the process technologies of preference can be integrated on-package. Join the UCIe Consortium to help advance chiplet integration and support interoperability within the ecosystem.

Cadence Targets Automotive Market Demands with UCIe

denali_mktg@cadence.com (Denali Software, Inc.) — Fri, 29 Sep 2023 06:57:00 GMT

Cadence has become a contributor-level member of the Automotive Working Group in the Universal Chiplet Interconnect Express (UCIe) Consortium. Last year, the Consortium ratified the UCIe specification, which was established to standardize a di...(read more)

How Do Robots Navigate?

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 13 Jul 2023 11:49:00 GMT

Have you ever been amazed by the graceful movement of robots and self-driving vehicles in unfamiliar surroundings? The latest technological advancements have introduced self-cleaning robots, autonomous vehicles with incredible navigation abilities. T...(read more)

Cadence Perspective: 224G SerDes Trend and Solution

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 10 Jul 2023 14:45:00 GMT

As an industry early mover to support the emerging 800G/1.6T networks, Cadence taped out the 224G-LR SerDes PHY IP on TSMC’s 3nm process at the beginning of the year and expects the silicon to arrive soon. The IP supports 1-225Gbps data rates with excellent BER at long reach (LR). The ever-increasing bandwidth requirement in hyperscale data centers is driving the rapid growth of high-speed I/O capability. The next-generation 224G serial link is here to enable the continually growing big data exchange in applications including Generative AI (GenAI) and Large Language Models (LLMs). Read this article to learn more about the 224G market trend and why Cadence’s 224G IP solution is leading the industry.

Figure 1: Simulated TX PAM4 eye of Cadence’s 224G-LR SerDes on TSMC’s 3nm process

Market Trend of High-Speed SerDes

GenAI and LLMs are disruptive technologies that will fundamentally transform how we live, work and play. To process the massive datasets that GenAI requires, the graphics processing units (GPU), tensor processing units (TPU), or other offload AI hardware in parallel and in sync must be interconnected using high speed links. Overall GenAI infrastructure is a massive network of high-speed links interconnecting all this necessary hardware.

This also implies that the network speed is one of the most significant limiting factors on how fast GenAI chatbots like ChatGPT or Bard can respond to an inquiry. This is just not about the compute capability but also the network link/bandwidth.

The increased demand for data bandwidth requires SerDes speeds to quickly move to the next-generation nodes. The following chart from IPnest describes the number of high-speed SerDes IP commercial design starts for the three data rates: 56Gbps, 112Gbs, and 224Gbps. What we can learn from this trend is that 224G SerDes adoption will start to increase this year with customer ASIC design starts, while the 112G and 56G SerDes IP demand will gradually decline.

Figure 2: SerDes IP Sales Count Trend from IPnest

Use Cases of 224G SerDes

Let’s review the use cases for the 224G SerDes in the chip-to-module (VSR), chip-to-chip (MR), and copper/backplane (LR) applications, which have similarities and differences from the 112G SerDes cases. The IEEE 802.3dj and OIF CEI-224G standards for 200G/lane are still evolving and need contributions from every aspect of the ecosystem, including SerDes, package, cable, and PCB vendors, to make feasible solutions. With data rates doubling at 224G, the PCB loss to connect the ASIC and the front-end panel is much worse at the higher Nyquist frequency than at 112G. This requires the improvement of PCB materials with lower loss, the connectors coming close to the host ASIC, adding more retimers on PCBs, or using flyover cable with much less loss than PCB. Even with all the improvements, the passive copper cable in the LR channel may not be able to exceed 1 meter and less than 2 or 2.5 meters in the 112G case. The current standard target for bump-to-bump insertion loss (IL) in copper cable (CR) and backplane (KR) implementations is about 40dB while C2M and C2C are between 25dB and 35dB.

Figure 3: 224G SerDes Use Cases for LR, MR and VSR

Cadence Advantages for 224G SerDes

Figure 4: Cadence 224G SerDes Advantages

As the first-to-market industry leader for DSP-based SerDes, Cadence has best-in-class 112G SerDes solutions, which built a solid foundation for the cutting-edge 224G SerDes IP. As indicated in the block diagram below, Cadence’s 224G SerDes IP is based on the ADC/DSP architecture similar to 112G, although each block needs a performance upgrade due to the doubling of data rate. The front-end AFE bandwidth (BW) must be increased. The analog-to-digital converter (ADC) must have reduced noise. The overall PLL jitter must be dramatically brought down because the signal UI is reduced. The DSP may need stronger equalization and the maximum likelihood sequence detection (MLSD) becomes more critical to get the performance that is needed. However, the challenge is not just to do all this, but to keep the pJ/bit better so the power cannot be doubled.

Figure 5: Design specifications of 224G SerDes versus 112G SerDes

The Cadence’s 224G SerDes PHY IP meets all the challenges above with superior BER performance at LR as well as optimal power and area. The IP can also support MR and VSR while the power savings can be configured for shorter reaches. Our 224G design has agility and flexibility as a lot of the parameters are moving targets that are not yet set by the standard. For example, while the industry has mostly agreed that PAM4 should be the modulation scheme for 224G at VSR and MR, the discussion has not fully settled on LR regarding PAM4 versus PAM6. Cadence’s 224G IP has the flexibility to support both PAM4 and PAM6 while the standards are evolving. We also have a very wide customer base and our support team can provide our customers with the best service.

The test chip silicon of Cadence’s 224G SerDes on TSMC’s 3nm process will arrive soon. This latest addition to the high-speed SerDes IP family further solidifies Cadence’s leadership position with high-performance connectivity IP offerings for hyperscale data centers, AI, and HPC applications.

For more information on the 224G-LR SerDes, please visit www.cadence.com/go/224g.

Cadence Showcases PCIe 7.0-Ready IP at PCI-SIG Developers Conference 2023

denali_mktg@cadence.com (Denali Software, Inc.) — Thu, 15 Jun 2023 01:20:00 GMT

PCIe 7.0 continues to progress through draft stage, IP enablement begins

The PCI-SIG announced that the PCI Express (PCIe) 7.0 specification has hit version 0.3 at the annual Developers Conference in Santa Clara on June 13, 2023. This represents a further doubling of the data rate to 128GT/s. The standard is expected to be finalized in 2025.

The PCIe standard has doubled the data rate approximately every three years

The 7.0 version will continue to use PAM4 signaling like 6.0 and maintain compatibility with prior versions with NRZ signaling for data rates 32GT/s and below. Cadence showcased its 128GT/s SerDes IP's receiver and transmitter capability at the event, demonstrating excellent electrical performance and margin. The demo was made possible with instrumentation from our partners Anritsu and Tektronix. Tektronix also hosted the same demo in their booth at the event, capturing the attention of a large number of attendees.

Cadence team demonstrating 128 GT/s SerDes IP to attendees

Cadence's first-in-the-industry IP subsystem for PCIe 6.0 was also a major draw. We showed off the electrical performance in our booth as well as with our partner Samtec. PCIe 6.0 is the first version of the spec to use PAM4 for signaling and Flit (flow control unit)-based architecture. Keysight Technologies showed off their exerciser/analyzer for PCIe 6.0 with our subsystem daughtercards. The Cadence subsystem IP for PCIe 6.0 has interoperated with the Keysight exerciser in both root-port and endpoint mode. Ali Ulas Ilhan from Cadence presented at the conference on interoperability-related topics for PCIe 6.0, highlighting the strides made by Cadence's design team in achieving these milestones. The electrical performance of the IP's receiver was also showcased with Samtec.

Cadence IP for PCIe 6.0 showcased at DevCon '23 (Cadence booth, Keysight Technologies, and Samtec demos. Ali Ilhan presenting at the conference)

Industry adoption of PCIe 5.0 continues apace. The Cadence IP for PCIe 5.0 is optimized for both power and performance and has achieved compliance in multiple workshops. The team showed off the subsystem IP for PCIe 5.0 operating on a commercially available motherboard, running stress tests that our customers typically use to qualify their products. Viavi Systems showed off their protocol analyzer for PCIe 5.0 with Cadence subsystem cards running eight lanes of PCIe traffic seamlessly at 32GT/s. The Cadence subsystem performance was so clean that the analyzer couldn't show error scenarios. They had to use an alternate card to demonstrate error cases!

Cadence IP subsystem for PCIe 5.0 demonstrated at DevCon '23 (Viavi Systems and Cadence demos)

Cadence continues to lead in PCIe development, offering solutions in advanced nodes for the latest versions of the standard. With a full suite of solutions encompassing PHYs, controllers, software, and Verification IP, Cadence is proud to be a member of PCI-SIG.

Cadence team at the PCI-SIG Developers Conference 2023

Cadence Collaboration with Kudan and Visionary.ai Enables Rapid Deployment of VSLAM and AI ISP-Based Solutions

denali_mktg@cadence.com (Denali Software, Inc.) — Mon, 22 May 2023 06:50:00 GMT

Are you confused while navigating new environments, especially in less optimum light conditions?

I am, and the problem worsens when lighting conditions are lousy and GPS connectivity is poor! Then, I try to locate my destination by looking at some landmarks.

Likewise, robots and self-driving vehicles use simultaneous localization and mapping (SLAM) and digital imaging to navigate unknown environments, even in the worst lighting conditions. SLAM and digital imaging work as an embedded vision for robots and self-driving vehicles as they make maps (especially while working indoors) of unknown environments while navigating through them. Such advancements incorporate different kinds of sensors and computer vision-based algorithms for SLAM, 3D object detection, tracking, and trajectory estimation. These computational imaging algorithms are very complex, involve extensive computational resources, and may lead to increased latency and power requirements. Digital Imaging is another major trend plagued by challenges such as low light, high/wide dynamic range (HDR/WDR) environments, and fast-moving objects. These are the most significant barriers to clear and crisp imaging. To best address these challenges, Cadence has signed up with Kudan and Visionary.ai for its Tensilica software partner ecosystem, bringing SLAM and AI image signal processor (ISP) to its processor cores. This partnership helps achieve the best performance in various segments such as advanced automotive, mobile, consumer and IoT, and drones. The proof is in the pudding; Cadence strengthens Tensilica Vision and AI software partner ecosystem for advanced automotive, mobile, consumer, and IoT Applications. While Tensilica Vision Q7 DSP helped achieve a nearly 15% speedup of Kudan's proprietary SLAM implementation pipeline compared to CPU-based implementation, Tensilica NNA110 accelerator helps customers implement a camera pipeline with a resolution of more than full HD at over 30fps.

How Do Robots/Self-Driving Vehicles Navigate? And Why Do We Need AI-Based Image Signal Processors (ISP)?

Empowering self-driving vehicles and robots with the ability to make this world a safer place is the talk of the hour. It involves navigating unknown environments, producing video even in the worst lighting conditions, and processing at the edge. SLAM empowers robots and self-driving vehicles with an embedded vision that helps construct or update an unknown environment map for inside-out tracking with embedded vision. It is commonly used in the robotics, drone, mobile, AR/VR and automotive markets. SLAM involves computationally heavy and a variety of linear algebra and matrix operations that require more time and processing under the hood, and it comprises feature detection, descriptor matching perspective transformation various filters.

GPUs are mostly floating-point machines, while a lot of these operations can now be done in fixed points, where DSP-type machines can benefit. So, you can get more parallel operations in the same register size with an integer. The usage of specialized processors such as GPU is limited due to performance capabilities and limitations such as high-power dissipation. The ISP functions are provided as hardware blocks in most systems with image/video functionality that offers high-performance throughput but suffers from issues like lack of flexibility or adaptability to current conditions. Also, hardware solutions with algorithms result in the loss of data captured by sensors. So, with AI now taking reign, image signal processors (ISP) can be found in a wide number of applications from smartphones to automotive and beyond.

How Cadence Tensilica Ecosystem Helps Automotive, Roots, IoT, and Mobile

A robust ecosystem (hardware and software) is essential to address the challenges mentioned above. Tensilica Vision and software ecosystem include more than 50 partners developing solutions for automotive, smartphone apps, IoT, software services and other segments. Cadence Tensilica IP-based devices help to run cutting-edge SLAM and AI ISP solutions efficiently and offer the best power-performance envelope. The ongoing innovations in Tensilica IP and architecture are critical for smartphone manufacturers and providers of IoT systems and next-generation connected vehicles. Cadence partnership with Industry leaders such as Kudan and Visionary.ai helps customers improve performance. Various benefits of these collaborations are as below:

Tensilica Vision Q7 DSP offers a 10X performance improvement and 15% speedup compared to CPU-based implementations of Kudan'c proprietary SLAM implementation.

"We're very excited about our partnership with Cadence and the opportunity to work with the Tensilica platform to accelerate Kudan's SLAM pipeline. Cadence's Tensilica Vision DSPs provide specialized instructions that optimize various stages of the SLAM algorithm, delivering significant gains with power savings to the end customer. We look forward to improving accessibility and adoption of our SLAM solution together."

-Juan Wee, CEO at Kudan USA

Visionary.ai's novel approach leverages AI to replace traditional hardwired ISP functions and enables real-time, high-quality video production, even in the most challenging lighting conditions.
Customers could implement a camera pipeline with a much higher resolution than full HD while working with over 30fps using Visionary.ai's efficient AI ISP over Tensilica NNA110.

"At Visionary.ai, we have developed a method of using AI to dramatically improve image quality in real-time, particularly in the most challenging lighting conditions. For this technology to reach its true potential, there is a need for fast and efficient neural network computations. Joining Cadence's Tensilica ecosystem will help ensure that our customers have a very competitive solution that runs on some of the most efficient vision and AI platforms out of the box."

Oren Debbi, CEO at Visionary.ai

Key Features Leading to the Adoption of the Tensilica Q7 DSP

Tensilica Vision Q7 DSP, The Cadence Tensilica Q7 DSP, is designed to meet the needs of applications using SLAM, enabling high-performance SLAM on the edge and in other devices.

With optimized instructions for faster performance on matrix operations, feature extraction, and the capability to provide a perfect balance of high performance and low power (essential to SLAM applications at the edge) along with convolutions, Cadence Tensilica Q7 DSP is poised to give the best performance. Cadence's Tensilica Vision Q7 DSP (digital signal processor), designed to enhance computer vision and AI applications, optimizes Kudan's SLAM pipeline— providing customers with a versatile, high-performance computing platform with SLAM capabilities for applications such as robotics. Click here for more details about Tensilica Vision Q7 DSP.

Key Features Leading to the Adoption of the Tensilica Neural Network Accelerator (NNA) 110

Cadence partners with Visionary.ai to achieve cutting-edge imaging technology. Tensilica processors are used for many AI applications due to performance, power, and what types of data are required (floating point, 8-bit, and so on). The NNA products include random sparse compute to improve performance, run-time tensor compression to decrease memory bandwidth, pruning, and clustering to reduce model size.

The Cadence Tensilica NNA 110 accelerator incorporates a custom hardware accelerator engine (NNE) coupled with a Tensilica Vision P6 or P1 DSP. The specialized compute block inside the NNA 110 hardware leverages features like random sparsity and tensor compression/decompression to provide an overall best-in-class embedded AI accelerator solution. Click here to read more about Tensilica NNA110.

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Cadence Demonstrates 112G-ELR SerDes IP on TSMC’s 3nm Process Technology

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 26 Apr 2023 14:55:00 GMT

The 3nm wave of technology is here! Cadence is proud to demonstrate its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s 3nm (N3E) process technology at the TSMC 2023 North America Technology Symposium this week. This is the latest addition to the Cadence 112G-ELR SerDes IP family. Riding the wave of More than Moore, FinFET transistors keep shrinking in TSMC’s 3nm process as they move towards system-in-package (SiP) designs. Combining the benefits of process technology advancement and Cadence’s best-in-class digital signal processor (DSP)-based SerDes architecture, the new 112G-ELR SerDes IP supports insertion loss (IL) of 45dB with exceptional power, performance, and area (PPA), making it ideal for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, switch fabric system-on-chips (SoCs) and 5G infrastructure applications.

Eye diagram of Cadence’s 112G-ELR SerDes on TSMC’s 3nm process (@ 106.25Gbps PAM4)

The ELR SerDes PHY is compliant with IEEE and OIF Long-Reach (LR) standards while providing additional performance margin beyond the standard specifications. The eye diagram above shows three wide-open eyes with good symmetry separating the four signal levels in PAM4 mode. The 3nm demonstration shows exceptional bit error rate (BER) performance of E-10 level with a channel of 39dB bump-to-bump IL, providing ample performance margin compared to the standard specification of less than 1E-4 at 28dB ball-to-ball IL.

Demo board and setup of Cadence’s 112G-ELR SerDes on TSMC’s 3nm process

The 112G-ELR SerDes IP also supports Medium Reach (MR) and Very Short Reach (VSR) applications with a flexible power-saving capability over different channels. The supported data rates range from 1G to 112G with NRZ and PAM4 signaling, enabling reliable high-speed data transfer over backplane, direct-attached cable (DAC), chip-to-chip and chip-to-module channels.

The SerDes IP incorporates an advanced DSP-based architecture with maximum likelihood sequence detection (MLSD) and reflection cancellation technologies that enable system robustness for lossy and reflective channels. MLSD is a powerful technique to improve BER and provides improved burst-error handling capability. Through proprietary implementation techniques, Cadence ensures that the power overhead of MLSD is minimal. The reflection cancellation technique cancels spurious, far-out reflections in a product environment with practical traces and connectors and thus provides robustness in BER outcomes.

Cadence’s 112G-ELR SerDes solution on TSMC’s 3nm process further solidifies our leadership position with high-performance connectivity IP offerings for hyperscale data centers, and customers can also enjoy the significant power and performance benefits associated with the TSMC 3nm process technology, the most advanced technology in both PPA and transistor technology.

For more information on the 112G-ELR SerDes, please visit www.cadence.com/go/112Gblog.

The Five Must-Have Features of Modern Automotive SoC Architectures

denali_mktg@cadence.com (Denali Software, Inc.) — Fri, 31 Mar 2023 01:03:00 GMT

Groundbreaking innovations demand state-of-the-art system-on-chip (SoC) architectures providing unprecedented high performance, safety, low power, security, and connectivity to support these new technologies. In this article, we will explore the five critical features of automotive SoC architectures that are essential for developing the next generation of passenger vehicles.(read more)

FMEDA-Driven SoC Design of Safety-Critical Semiconductors

denali_mktg@cadence.com (Denali Software, Inc.) — Wed, 18 Jan 2023 17:48:00 GMT

Written by Francesco Lertora and Robert Schweiger

1.1 Introduction

The growing complexity of electronics in modern cars is driving the automotive industry to adopt even more stringent processes throughout the supply chain. The lack of tools and methodologies to enforce a traceable safety lifecycle and exchange of safety-relevant information has created the need for an integrated design flow that addresses the safety requirements of the semiconductor industry and can be used across the supply chain.

This requires a new safety methodology, providing a seamless flow that closes the gap between safety analysis and typical chip design tasks such as safety verification and safety-aware implementation. Furthermore, as the development of safety-critical semiconductors and IPs is a complex and compute-intensive task, the automation of this process is crucial in increasing confidence in the safety methodology and improving productivity.

1.2 Enhanced Safety Methodology

Commonly used safety analysis tools such as FMEDA are not integrated with IC design tools or flows. Therefore, there is no formal way to describe and propagate the safety intent captured in FMEDA to the IC design flow driving safety tools accordingly (top-down methodology). Conversely, there is no formal way to back-annotate simulation-based data from a fault injection campaign into the FMEDA (bottom-up methodology) to replace estimated failure rates with more accurate values.

Some key enhancements are necessary to support a top-down and bottom-up safety methodology fully:

Tight integration between FMEDA and safety IC design flows
Formal description to specify the safety intent of the chip that all IC design tools support and can adhere to
Import of the chip design data to establish a formal connection between FMEDA and chip hierarchy
Back-annotation of simulation results into the FMEDA to improve the accuracy of estimated metrics

Cadence has introduced the new Midas Safety Platform to close these gaps. The Midas platform is seamlessly integrated with all Cadence IC design flows to enable an FMEDA-driven design, analysis, verification, and implementation of analog/mixed-signal and digital semiconductors and IPs. The integrated framework provides a workflow that guides the safety engineer through all the key steps, from FMEDA creation, safety analysis, safety verification and safety-aware implementation.

1.3 Supported Industry Standards

Despite the ISO 26262 standard, the lack of safety standards in formal ways to describe safety intent, including supported tool flows, has led to various in-house developed safety solutions mainly using spreadsheets and scripts. However, standards bodies such as Accellera and IEEE have formed dedicated working groups to address these safety requirements in establishing an adequate safety standard. The Midas platform, as the Cadence Functional Safety Solution, provides a safety framework with various interfaces meant to work within an ecosystem of tools and flows (Figure 1).

Figure 1: Cadence Midas Safety Platform to enable FMEDA-driven safety methodology

The Midas platform is a modular and open solution that can be easily tailored to different applications and use cases while having solid foundations in existing standards for functional safety. This is primarily why the Midas platform integrates a safety analysis engine supporting the ISO 26262 (automotive) and IEC 61508 (industrial) standards.

The safety analysis engine can leverage estimated design information (e.g., area, number of flip flops or memory bits) provided by the user or use chip design data of Cadence IC design tools such as Genus (Synthesis), Innovus (Place & Route) or Xcelium (Fault simulation) to calculate the hardware safety metrics automatically.

In addition, Midas provides a dedicated engine for the Base Failure Rate (BFR) calculation according to the reliability model for integrated circuits defined in the IEC TR 62380 standard. The BFR can be calculated after entering information such as semiconductor process technology, custom mission profiles, and package information.

1.4 FMEDA Creation

Safety engineers can start with an “Architectural FMEDA,” an early-phase exploration of different safety architectures to identify the optimal set of safety mechanisms to achieve the safety goals.

To set up the FMEDA, it is necessary to define the parts and subparts representing the functional building blocks of the SoC to create the FMEDA hierarchy (Figure 2). It is also necessary to define one or more failure modes for each part and subpart and map a safety mechanism. If no chip data is available, the base failure rate can be equally distributed across all failure modes. Once the architectural FMEDA is set up, the safety analysis engine can calculate the hardware safety metrics (SPFM, LFM, PMHF).

A “Detailed FMEDA” can be performed once chip design data becomes available. After importing the chip design into the Midas platform, the design hierarchy, including all design blocks, show up as a hierarchical tree (Figure 2). Design instances can now be easily mapped per drag-and-drop to the FMEDA hierarchy. Chip design data such as design instances, numbers for area, gates, and flops are assigned automatically to all failure modes, and the BFR distribution can be adjusted accordingly. Finally, everything is prepared to set up the fault injection campaign in the Cadence Verisium Manager Safety.

Figure 2: FMEDA GUI and set-up

After the safety verification is completed, the simulation results can be back-annotated to the Midas platform. As the failure distribution and diagnostic coverage values are now based on real design and simulation data, the recalculated HW safety metrics are much more accurate.

1.5 Unified Safety Format

The Unified Safety Format (USF) is a set of commands to define and verify the functional safety intent in electronic design.

The functional safety intent includes the information required to model, specify, analyze, implement and verify safety-critical systems, semiconductors, and intellectual properties (IPs), enabling the portability of the same information across various commercial EDA tools.

USF facilitates the automation of safety analysis and becomes the common framework to design, verify, and implement safety-critical systems. The safety analysis engine is also available via a command line interface, which makes the Midas platform fully scriptable and supports different levels of automation.

Leveraging USF, safety engineers can model the FMEDA and its effects on the behavior of a system (failure modes) by describing failure modes, including safety mechanisms and their physical implementation.

As with USF, the FMEDA process can be fully captured, and USF can also be modified and reused to automate the FMEDA creation of other projects.

Figure 3 shows a simple example of USF commands describing an architectural FMEDA (design information is estimated at the failure mode level) and detailed FMEDA (design information is gathered from a real design).

Figure 3: USF example – architectural and detailed FMEDA

1.6 Midas Safety Platform

The Graphical User Interface of the Midas platform integrates various functional safety tasks:

Safety analysis authoring (design partitioning, failure modes definition, safety mechanism selection, and failure modes mapping);
Safety report generation and export of relative metrics (e.g., Single Point Faults Metric, Latent Faults Metric) and absolute metrics (e.g., Probabilistic Metric for Random Hardware Failures)
Safety configurations to create, save and restore different safety scenarios where one or more parameters can be changed (e.g., add or remove safety mechanism to analyze the effect on the diagnostic coverage);
Support custom attributes mapping to a safety object (e.g., parts, subparts, failure modes, and safety mechanisms).

1.7 Safety Verification Flow

The Midas platform leverages the central role of Cadence as an EDA vendor, providing a safety solution and safety cockpit to enable FMEDA-driven safety verification and safety-aware implementation.

The tight integration of the Midas platform with the Cadence Safety Verification flow represents a flexible verification solution, enabling the validation of assumptions made in the safety analysis phase.

The Verisium Manager Safety plays a critical role in the verification process. It provides a unified fault campaign management to automate and manage complex fault injection campaigns driving all safety engines such as Xcelium, Jasper Functional Safety Verification (FSV) App, Spectre^® AMS Designer, and Spectre.

The Verisium platform covers tasks such as fault campaign execution, test selection and ranking, fault classification, coverage, fault debugging, fault campaign reporting, and back-annotation of simulation results into the Midas platform.

After fault injection, the safety verification flow starts with fault analysis using the Jasper FSV App. By applying structural and formal fault analyses, the Jasper FSV App can identify untestable, unobservable, and equivalent faults that can be ignored in the subsequent fault simulation. This significantly reduces the fault list, accelerating the overall safety verification process. After fault analysis, the Xcelium Safety App simulates all remaining faults, leveraging the serial or concurrent fault simulation engines.

Further, the Midas platform also integrates with the Spectre Simulation Platform and Legato Reliability Solution, addressing analog and mixed-signal fault identification and simulation. Similar to the digital safety flow, the Midas platform can collect analog design information from the Spectre Simulator.

1.8 Safety-aware Implementation Flow

The Midas platform enables an FMEDA-driven safety-aware implementation, where the synthesis and Place & Route tools work in tandem.

USF allows the definition of safety mechanisms such as dual-core lockstep, safety islands, triple modular redundancy (TMR), logic isolation, and others. Once defined, the safety mechanism can be generated by the Genus Synthesis Solution. A USF file describing the implementation of the safety mechanisms can be saved and read by Innovus to drive the physical implementation accordingly.

1.9 Conclusions

The Midas Safety Platform is the first solution that truly enables an FMEDA-driven safety methodology for analog/mixed-signal and digital. The Midas platform is the unified cockpit across all Cadence safety flows, connecting FMEDA with SoC safety verification and safety-aware implementation. All Cadence safety flows are leveraging USF as the foundation to define the safety intent enabling automated safety-aware design, verification and implementation.

For more information on Midas please visit: https://www.cadence.com/en_US/home/solutions/automotive-solution/functional-safety.html

or watch the short overview video on the Midas Safety Platform: