Power management in IC design is loaded with exciting new developments. There have been attempts to solve power-related  issues by altering the overall semiconductor process, biasing selected portions of a design, implementing various power distribution structures, introducing power gating, changing on chip network architectures, introducing microprocessor-based power channels, introducing energy processing units, and even more. […]

Doing business with Sonics has never been easier than in 2017. We just launched a re-designed web site that provides everything you need to know about our EPU and NoC technologies in a quick and easy to find format. Whether you are a power architect looking to save energy or an SoC designer searching for […]

Why everyone needs to start taking power more seriously, and what you can do about it. Energy is a finite resource, which means it’s not someone else’s problem. It’s everyone’s problem. This isn’t just another doom and gloom prediction. Energy consumption has been rising steadily for decades. Unfortunately, it has been increasing at a faster […]

Thanks for visiting us. After 20 years of business success serving the on-chip communication needs of system architects and SoC designers, Sonics has turned its attention to the issue of power management. We have expanded our technology and product portfolio to address the critical issue of saving on-chip power. Every design team and engineer developing […]

Complexity and flexibility are the real drivers of fabric choice, not the number of initiators and targets. Since I first helped introduce the concept of applying networking techniques to address SoC integration challenges in 2007, I have been asked many hundreds of times how to determine when and where to best use an on-chip network […]

Make vs. buy isn’t as simple a decision as it might appear. When companies consider purchasing Semiconductor IP (SIP), they often have a strict procedure for evaluating third-party vendors and their products. If they don’t have a set way of evaluating IP, the Global Semiconductor Alliance (GSA) has developed a Hard IP Licensing Risk Assessment […]

Why a methodology for developing software is now required in hardware. History repeats itself, but frequently not in the exactly the same place. The problems faced by system engineering teams today rising complexity, shorter market windows and more issues involving interactions that affect everything from dynamic power and leakage current to electromigration and finFET design […]

On Semiconductor Engineering, Randy Smith discusses the four primary failure modes associated with NoCs.

The past year was a renaissance for Sonics in the public eye. With a high volume of company announcements, product launches, customer wins, and partner initiatives, the company generated a steady stream of positive news and points of view from both business and technology perspectives. As we bid 2014 goodbye, we thought it appropriate to […]

Earlier this month I had the distinct pleasure of attending the EDA Consortium’s (EDAC) prestigious Phil Kaufman award dinner. This year’s winner is Lucio Lanza, managing director of Lanza techVentures, LLC. Lucio is an EDA industry legend. We used to bump into each other often in the Cadence hallways after both of our companies had […]