AMD Developer Forums - General Discussions

Technology question

Yozh123 — 2009-11-08T13:45:51 -05.00

Hello,

where can I find an information on the opteron CPU technology such as what is a switching delay in typical inverter inside the processor (in particular - in its ALU)?

Thank you in advance.

Multiplication instruction (MUL)

Yozh123 — 2009-11-05T03:00:43 -05.00

Hello,

does anyone have public information on how many CPU/clock cycles it takes for latest AMD CPUs to perform 32-bit multiplication? There should be a document listing all the durations for every command, but I can't find it...

Thanks!

Distribution Channels

vanissam — 2009-11-04T15:43:26 -05.00

Hello,

I am a student from York University, and I'm doing a marketing plan based on your company. I was wondering if someone is able to aid me in understanding your various levels of distribution channels and their logistics.

I am aware the website has information on types of distributors and their regions however, I need more depth in the information. (ie. what exactly is a master distributor? How is your product transfered in terms of transportation? How many distribution channels are there, in terms of distributors --> wholesalers --> other resellers --> retail stores??)

Is there anyone I can contact or if you can assist me in understanding this?

Thank You!

Page Walk Cache on NPT

jhuell — 2009-11-03T16:41:07 -05.00

As you know, AMD-V has some versions like NPT only or NPT with Page Walk Cache. Is there somebody who knows which one has NPT with Page Walk Cache?

Thanks

ati firegl v3400 drivers for windows 7

chetan — 2009-11-01T03:32:07 -05.00

hi, i have firelgl v3400 and have installed windows 7 recently but i was not able to find the drivers for windows 7.. it would be very helpful if some one would guide me through this. thank you

5870 quadfire user video

Bodar — 2009-10-25T22:51:17 -05.00

Check it out. Awesome!

http://www.guru3d.com/news/radeon-hd-5870-quadfire-user-video

Where is doc about prefetch implementation?

mrolle — 2009-10-22T15:54:42 -05.00

I want to know how prefetch is implemented on the Phenom in particular, but also for other processor models.

In particular, (1) how many streams can be active, (2) automatic hardware prefetch and how to control it, (3) what happens if address not in TLB and/or page table.

The embedded memory controller is supposed to have a data sheet, but I can't find one. A pointer to that would also be appreciated.

Thank you.

Does the processor have special behaviour for multiple prefetch on same cache line ?

DevProg — 2009-09-29T20:33:08 -05.00

Does the processor have special behaviour for multiple prefetch on same cache line ? for example: mov eax,[ptr] prefetchnta [eax] prefetchnta [eax+4] prefetchnta [eax+8] prefetchnta [eax+12] prefetchnta [eax+16] prefetchnta [eax+20] Does the Load buffer allocate entries of these prefetches?

Are AMD going to counter the Intel i5/i7 s1366 price2performance-ratio soon?

chiron — 2009-09-24T09:07:07 -05.00

I'm considering buying a new system for the latest musicplugins&games.

But now that the Intel i5 (i7-performance for not much money), should I go for the i5, with cheap dualchannel mem mobo's,and the i5 itself cost a lot less than the Phenom II 940/965 and CRUSHES the AMD in tests.

Is AMD going to slash their prices (considerably) for the Phenom II range in the near future, or are they giving away the homemarket to Intel? (Again) :-| I've always used AMD systems,and I'd like to continue to do so in the fiture, but the i5's performance have made me think twice at the current Phenom II prices. If AMD is gonna stand a chance, they'll have to cut CPU-prices FAST, not after people have ordered their xmas-parts/systems!

So, does anyone here know if AMD is lowering Phenom II prices soon, or should I just go for the Intel i5?

Which AMD CPU support Virtualization??

ph7 — 2009-09-21T18:00:11 -05.00

From products.amd.com it seem most Athlon and even a lot of Phenom don't support AMD-V??

no AMD-V CPU

Detail page for AMD Phenom™ X4 9950

Phenom X4 9550

For AMD Athlon™ II X2 250

Athlon II X2 250

This can't be right!

Why is my memory so so slower than specified ???

vlad777 — 2009-09-16T19:43:47 -05.00

I am not using prefetch and movnt(q).

Why is my best result well bellow 2GB/s? (about 700 MB/s)
Why is my worst result as low as 18Mb/s?
What should I know about hardware architecture
to understand this?Links,Docs?

(note: For sequential movntq i get 1748.86 MB/s.)
(possible explanations: cache is getting in the way,memory address lines are multiplexed ....??)

------------------------------------------------------------------------
Cpu: AMD Thorton 2 GHz (socket A)
Cache: L1 64KB D/I L2 256 KB full speed
Memory: DDR1 133/266 MHz FSB capacity 1.2 GB speed (should be) 2100 MB/s
Chipset: VIA KT400

------------------------------------------------------------------------
Test algorithm:
Addres equals base address.
Address is inkremented by (constant) jump value
and when it reaches the end of the memory chunk
it resets to incremented base address (by 1).
The process then repeats
until base address increment is equal to jump
or is equal to memory size chunk.
(
every n_th address is read then every (n_th)+1
then every (n_th)+2 and so on... until every (n_th)+(jump-1)
thus reading the whole memory chunk
)
Memory chunk size is 4MB.
Memory is tested for speed with diffrent jump values.
note: Memory test code with memory transfers commented out
is about the same speed for diffrent jump values.

-------------------------------------------------------------------------
Test code:

#include<windows.h>
#include<stdlib.h>
#include<stdio.h>

void test1(long* m,long jump){

_asm{
mov edi,[m]
mov esi,edi
add esi,4194304
mov ecx,edi
mov ebx,0
mov edx,jump
shl edx,2
}

ll:
_asm{
mov edi,ecx //mov edi,[m]
add edi,ebx
}

l:
_asm{
mov eax,[edi]
add edi,edx
cmp edi,esi
jb l

add ebx,4
cmp ebx,edx
jae k
cmp ebx,4194304
jae k
jmp ll
}

k: ;

}

void test2(long* m,long jump){
long a;
long adr=0;
long pass=0;

while(pass<jump && pass< 1048576){
adr=pass;
   while(adr<1048576){    // 4194304/4
   a=m[adr];
   adr+=jump;
   }
pass++ ;
}

}

void main(){

double cur,best=0,worst=3000;
int j;
long i;
int tick;
FILE *f;
long *m=(long *)malloc(4194304);
f=fopen("test2.txt","w");

for(i=1;i<=524288;i<<=1){

tick=GetTickCount();
for(j=0;j<1000;j++) test2(m,i); //--------------------------
tick=GetTickCount()-tick;

cur=(double)( 4194304/((double)tick/1000000)/(1024*1024) );
if(cur>best)best=cur;
if(cur<worst)worst=cur;
printf("\n speed=%5.2f MB/s jump= %d *4 bytes",cur,i);
fprintf(f,"\n speed=%5.2f MB/s jump= %d *4 bytes",cur,i);
}

   printf("\n\n best=%5.2f MB/s worst=%5.2f MB/s \n",best,worst);
fprintf(f,"\n\n best=%5.2f MB/s worst=%5.2f MB/s \n",best,worst);
fclose(f);
}

--------------------------------------------------------------------------
Test results:

test1 assembler:

speed=644.85 MB/s   jump= 1 *4 bytes
speed=453.10 MB/s   jump= 2 *4 bytes
speed=307.69 MB/s   jump= 4 *4 bytes
speed=190.90 MB/s   jump= 8 *4 bytes
speed=101.79 MB/s   jump= 16 *4 bytes
speed=109.40 MB/s   jump= 32 *4 bytes
speed=105.35 MB/s   jump= 64 *4 bytes
speed=96.93 MB/s   jump= 128 *4 bytes
speed=90.36 MB/s   jump= 256 *4 bytes
speed=80.65 MB/s   jump= 512 *4 bytes
speed=71.93 MB/s   jump= 1024 *4 bytes
speed=67.32 MB/s   jump= 2048 *4 bytes
speed=37.19 MB/s   jump= 4096 *4 bytes
speed=18.85 MB/s   jump= 8192 *4 bytes
speed=18.79 MB/s   jump= 16384 *4 bytes
speed=18.80 MB/s   jump= 32768 *4 bytes
speed=201.89 MB/s   jump= 65536 *4 bytes
speed=475.85 MB/s   jump= 131072 *4 bytes
speed=715.05 MB/s   jump= 262144 *4 bytes
speed=677.28 MB/s   jump= 524288 *4 bytes

best=715.05 MB/s worst=18.79 MB/s

test2 c++ :

speed=436.87 MB/s   jump= 1 *4 bytes
speed=261.76 MB/s   jump= 2 *4 bytes
speed=139.81 MB/s   jump= 4 *4 bytes
speed=101.11 MB/s   jump= 8 *4 bytes
speed=71.99 MB/s   jump= 16 *4 bytes
speed=98.35 MB/s   jump= 32 *4 bytes
speed=95.42 MB/s   jump= 64 *4 bytes
speed=89.89 MB/s   jump= 128 *4 bytes
speed=71.87 MB/s   jump= 256 *4 bytes
speed=68.05 MB/s   jump= 512 *4 bytes
speed=64.61 MB/s   jump= 1024 *4 bytes
speed=67.67 MB/s   jump= 2048 *4 bytes
speed=37.14 MB/s   jump= 4096 *4 bytes
speed=18.79 MB/s   jump= 8192 *4 bytes
speed=18.75 MB/s   jump= 16384 *4 bytes
speed=18.77 MB/s   jump= 32768 *4 bytes
speed=195.71 MB/s   jump= 65536 *4 bytes
speed=198.45 MB/s   jump= 131072 *4 bytes
speed=316.83 MB/s   jump= 262144 *4 bytes
speed=460.46 MB/s   jump= 524288 *4 bytes

best=460.46 MB/s worst=18.75 MB/s

(What does random access memory stand for again?)

Does ATI FireGL support even exist?

jcclow — 2009-09-14T23:29:52 -05.00

I have to admit...I'm furious! I have spent the last three days trying to find some kind of support for my new FireGL V5600. The CD that came with the video card gives an address of www.ati.com/online/registration and a unique ATI CustomerCare Product Serial Number that I'm supposed to use to register my new card and get support. However, when you enter that address, you just get dumped to the generic AMD drivers site. The card is not working with my PC and ATI doesn't even seem to exist to offer support. Does anyone here know how to get the support that is bragged about in all the reviews of this card? Thank you and I apologize for my tone, but this is uncalled for.

Not to mention the links provided in this forum for ATI GPU support (http://support.ati.com/ics/support/default.asp?deptID=894) are all broken too.

Shanghai/Istanbul intra-chip cache coherency behavior

dkanter — 2009-09-04T16:15:11 -05.00

Suppose you have a single socket system (desktop or server is irrelevant), with a 4 or 6 core CPU. I'm trying to understand how different cores on the CPU will share/provide cache lines to one another.

Suppose a clean cache line, L, is only held in the L1D cache for core0 in the CPU, and not in the L3.

If core1 tries to read data from L, it will miss in it's L1D and L2 caches. It will probe the L3 cache, and should probe the other L1D and L2 caches in the CPU (to see if the line is present and modified).

Who will satisfy core1's request?

1. It could get the data from the memory controller, which would be slow.

2. It could get the data from the L1D cache for core0, which should be faster.

It seems like #2 would make the most sense. Can someone from AMD explain which is the case? It's possible that this is not a yes/no question and is more complex, and if so, I'd like to understand what will determine the answer (e.g. would the probe filter change behavior at all).

Added: I just checked the BIOS and kernel dev guide and it appears that there is a performance counter "EventSelect 043h Data Cache Refills from the Northbridge" and the unit mask selects which of the 5 states the line is in...this seems to imply that a clean line could be filled from another L1D on the same die, but it'd be nice to have this verified.

Thanks,

David

phenom II x4 965 BE hypertransport bug ???

maxreason — 2009-09-02T07:12:35 -05.00

I built a new system with phenom II x4 965 BE and gigabyte motherboard GA-MA790FXST-UD5P running windows xp 64-bit edition, but the system would freeze every 1 to 20 minutes at random times (including when no task was running and nothing was happening).

I'll skip the 3 days of careful and thorough tests I ran, but it included running memtest86+ for hours from boot CD generated (zero errors), removing everything except video card from the motherboard slots, trying other memory modules, underclocking the CPU from 3.4GHz to 2.4GHz, underclocking the 1600MHz memory modules to 800MHz, and so forth.

For some odd reason the BIOS sets the northbridge/hypertransport speeds to 2000MHz instead of the 2600MHz that this CPU and chipset should support, so that should have been very conservative. Nonetheless after I had tried everything else I downshifted via BIOS the northbridge/hypertransport speeds from 2000MHz to 1600MHz --- and the system became completely reliable, stable, solid thereafter (for 2+ days so far).

Thinking the motherboard and/or northbridge chipset must be defective (slower than specification) I ordered a new motherboard. I figured this would surely solve the problem. Today I got the new motherboard and found it has ***exactly*** the same problem.

My question is --- where is the bug?

I am certain AMD chip testing tests the hypertransport bus on their CPUs at the full 5200MT/s hypertransport v3.0 speeds, so I tend to believe the CPU is not defective.

That leaves two possibilities that I can think of:

#1: Something is fundamentally wrong with this motherboard.

#2: Some code in Windows XP 64-bit edition malfunctions when the northbridge/hypertransport speeds exceed 1600MHz.

To me, #1 seems quite unlikely for the following reason. I chose this motherboard because most reviews of the Phenom II x4 965 BE CPU were performed on this motherboard --- and none of them reported any problems with flakiness in general or the northbridge/hypertransport in particular. In fact, many of these reviews overclocked the various parts of the system to see what kind of performance they could achieve.

That leaves #2, which seems somewhat unlikely too --- but what other possibilities are there? Am I missing some more likely possibility? Obviously there is one other possibility:

#3: The CPU chip I have was not properly tested, or malfunctioned within the first 15 minutes of running in my system. That seems highly unlikely to me, but it is possible.

Q1: Does anyone else run this combination of <CPU, motherboard, OS> with northbridge/hypertransport at 2000MHz to 2600MHz (or higher)?

Q2: Does anyone see any other possibilities that did not occur to me?

PS: The CPU temperature never exceeds 41C, the system temperature never exceeds 41C, the GPU temperature never exceeds 51C, and the system has lots of fans and excellent airflow (and the fans always run at full speed). The problem is no more likely to occur with lots of CPU activity versus minimal activity.

##### system specifications #####

motherboard: one gigabyte GA-MA790FXT-UD5P
CPU: one 3.4GHz AMD phenom II x4 965 BE (black edition)
DRAM: four mushkin 996601 modules (4 x 2GB DDR3-1600MHz @ 7-7-6-18)
video: one evga nvidia GTX 285 with 2GB VRAM
disks: two seagate 1TB SATAII drives (ST31000528AS)
disks: one western-digital 1TB SATAII drive (WD10EADS-00M2B0)
CDDVD: one NED CD/DVD burner (ND-3540A)
power: one coolmax greenpower 950W (CUG-950B)
CPU-cooler: zalman CNPS9700
fans: eight 80mm ball-bearing fans running constantly at full speed

NOTE: the DDR3 memory is running at 800MHz to 1333MHz @ 9-9-9-24
NOTE: often the tests were run with only one hard disk drive connected

PS: Reply here or send reply to <maxreason at gmail dot com>.

ATI Problem , the distance will be blurred

bhonam — 2009-09-01T12:38:53 -05.00

I am using ATI 4870
I don't understand that why the distance will be blurred in games.

When I change it to the Nvidia graphic card , the game setting has not changed
the problem was solved.

How can i fix this problem ?

Picture:

http://www.hkepc.com/forum/attachments/month_0908/20090829_1245c7f8701cbfe059e6WnpvoLbv8yqo.jpg

http://www.hkepc.com/forum/attachments/month_0908/20090829_5f7b60816642eceb0cfcRvAzaYjJlCVN.jpg

how can I optimize the memory managing of linux which is CPU+GPU

taocb — 2009-08-31T22:23:44 -05.00

hi,

I want to optimize the memory managing of linux which is CPU+GPU?but I don't know what I do,can someone give some idea?

CPU + GPU, possible????

NathanOSY — 2009-08-31T11:52:11 -05.00

Hi all, i am developing a new project to compete with Intel's Larrabee GPU project. Currently i still studied inside the University but i kept thinking of researching new tech for the future. Still, i am not working with any semiconductor factory yet.

I also design the blue prints of the next phased GPU (only 50% completed and basic phase).

What had crossed my mind is should a CPU and GPU hybrid together??? Any comments will be appreciate.

Edit: Turned off emoticon parsing

Problem with kernel Attribute or domainSize

slice4e — 2009-08-29T15:12:39 -05.00

I have written an implementation of a reduction in Brook+ 1.4 - comparing two matrices A and B and outputting if they are the same or not.

My code works as follows:

1) One thread scans down one column of A and B and compares the elements.

2) Using a Attribute, I define a thread goup of 64 threads. In the second step, after those 64 threads have scanned the columns, they communicate using local data store and reduce their results to a single output.

3) I have enhanced this implementation, by using creating more threads and each thread scans only part ways down the column. To do this, I use kernel.domainSize( ... ). I also use float4, so each thread essentially scans 4 columns.

My Problem:

My code works perfectly fine the first iteration. However, if I run it within a loop with several iteration, it fails to produce the correct results. After some debugging - it seems to me that the second time around my threads are not created properly ( printing their thread ids does not make any sense the second iteration). I think that this has something to do with Attribute or Domain and I cannot figure it out for 2 days now.It also seems that my output stream has to be the same size as my domain - for my code to work. In other words I think that domain does not work.

I have attached my code. Any help will be appreciated.

My code works per

Opteron memory consistency model info?

jtsmith581 — 2009-08-27T15:13:06 -05.00

Where can I find a detailed description on Opteron's memory consistency model, including read/write combinations across multiple pages and 'home' memory controllers. As far as I understand the coherency model (MOESI), writes are effectively serialized to a given cache line between multiple cores, but I don't understand what allows shared memory objects larger than 64 aligned bytes to behave properly (unless barriers are thrown around almost everywhere). If I have cores A-D on separate sockets where A writes to pages hosted in RAM off each, and B wants to read a consistent image of the aggregate output, how is this guaranteed? For example, is it strictly necessary to used locked instructions/memory fences for shared ring buffers? Would anything like a copy-on-write tree be consistently viewable without forced queue flushes across an entire system? If at all possible, I'd like an answer more substantial than 'it just works if you do X.' Thanks for any help!

--Jeff

how to delete my developer account?

chromos — 2009-08-25T11:23:31 -05.00

it's impossible for a human to find out where he can delete his account? so whom can I ask?

hi

jacob281 — 2009-08-24T06:15:41 -05.00

Hello guys, i m kinda new here so i thought i should introduce my self. my name is jacob and i m from the UK.

i m kind of new in development line, but i m working hard to be pro.

wish me luck.

HD2400 / rv610 power managment

kuz — 2009-08-16T05:37:37 -05.00

Hello,

i'm using linux and have desktop with HD2400. Currently HD2400 is very hot. No X11 is running, just plain console. I'm searching a way to cool down my HD2400. I have 42589_rv630_rrg_1.01o.pdf, but there is'nt enoung information about power managment.

I tried to setu up GPU_COUNTER_CLK to 1 in GENERAL_PWRMGT register, but this seems doesn't help.

Changing SCLK_PWRMGT_EN in SCLK_PWRMGT_CNTL and MPLL_PWRMGT_OFF in MCLK_PWRMGT_CNTL doesn't help too.

Is there any recomendations/documentation how to setup device for low power mode?

Supported payload sizes

mbouzaidi — 2009-08-13T07:20:02 -05.00

Dear AMD,

According to the RS780 and RS690 ASIC Family Register Reference Guide, the only supported payload size for PCI express TLPs is 128 bytes. Is this the same for all current AMD northbridges? Or are there some that support different payload sizes?

Thank you.

Who is the brand ambassador of AMD ?

sam890060 — 2009-08-11T20:40:05 -05.00

Who is the brand ambassador of AMD ? Any celebrity ? Sportsman? Politician ?

Earlier I saw viswanathan anand in one AMD !

Who is the latest ambassador ?

Any AMD industry/company in India ?

sam890060 — 2009-08-11T20:36:38 -05.00

I'm doing my engineering in computer science and I would like to go to AMD company for Industrial Visit (IV). I'm in South India. May I know where AMD development centre or company is ? In India?

Need "BIOS and Kernel Developer's Guide" for 10h Family CPUs ( Phenom I/II etc)

Brane2 — 2009-08-06T04:54:55 -05.00

I'm unstisfied with memtest86+ and would like to optimize,rework and expand it, but in order to da that properly I neeed more info about extra hardware on CPU ( PLLs, memory controller, HT links etc).

"BIOS and Kernel Developer's Guide" contains that kind of info, but version for Phenom doesn't seem to be available...

It would be nice if I could get ACC- related info, but I suppose this is deeply in the "wet dreams" area...

Can anyone help ?

Geode LX800 and CPU frequency scaling

ebianchini — 2009-08-03T09:36:47 -05.00

Does anybody knows if AMD Geode LX800 supports CPU Frequency Scaling?

I've search through all AMD site without success in find some information about this.

My problem is that I have to give to my software some way to control the CPU frequency.

My environment:
Motherboard: Axiomtek ETM620
Processor: AMD Geode LX800
OS: Linux Debian 4 Kernel 2.6.18
Software developed in Java (if possible will control CPU frequency using some JNI)

Thanks all.

Which will be the future processor ?

sam890060 — 2009-08-02T04:01:12 -05.00

Which will be the leading processor in future ? Intel or AMD or any other.. if so why?

Regards,

AMD suits best for which platform?

sam890060 — 2009-08-02T03:59:12 -05.00

AMD suits for which platform excellently.. like linux, mac or windows?

Regards,

Edit: Removed advertising

Can you use AMD software on Zii platform

dhealy — 2009-07-30T13:02:42 -05.00

Recently announced Zii platform is, according to its website, open. The company behind it is 3DLabs, or whatever they are called now, so no surprise there is hardware OpenGL support, among other things. The hardware looks iphonesque but it seems to be much much powerful (multicore ARM), possibly able to serve as basis for gaming consoles or wireless streamers, skypephones or simply put: modern day palmtops (except not from Palm). I was wondering if it would be possible to use GPU PerfStudio and other AMD apps on it. Any idea?

Hardware Benchmarking tools

prako — 2009-07-16T03:37:28 -05.00

Hi,
Im using AMD opteron 4-core PC. When i parallelise(Using OpenMP) and run a serial legacy application on the 4-core i get very inconsistent results when compared to the results on a single or dual core. I want to benchmark my PC to know how well the 4-cores are being utilised and to check the load on each core. Could someone please suggest some good tools that would give the above information as well as the information on the memory usage etc....

Thanks

How to Preserve Code Formatting and Indentation

pnolte — 2009-07-13T14:37:24 -05.00

Scroll down for an update.

Greetings,

A few of our members have asked how to post code snippets without losing indentation and formatting. There are actually two ways that you can preserve your code indentation/formatting when posting to our forum.

1. The first method is the easiest. In your forum profile, select the WYWIWYG editor instead of the HTML editor. From there, you can simply copy/paste your code, and the indentation/formatting will be preserved. For example:

default
{
    state_entry()
    {
        llSetStatus(STATUS_PHYSICS, TRUE);
        llSetBuoyancy(1.1);
        llSetStatus( STATUS_DIE_AT_EDGE, FALSE);
        llSetTimerEvent(gap);
        llResetTime();
    }
    on_rez(integer delay)
    {
        buoyancy();
    }

}

To select the WYSIWYG editor, visit http://forums.amd.com/forum/profile.cfm?FTVAR_PROFILEPAGE=2 and then check the WYSIWYG Editor button.

2. If you prefer using the HTML editor, then you can enclose your code within ...tags. Again, this will preserve your formatting/indentation.

In either case, you should always check the Do not parse emoticons checkbox, which prevents code elements from being converted into smileys.

Which SDK for basic frame grabbing under Linux?

MooseDrool — 2009-07-10T15:37:10 -05.00

Intended application is frame grabbing (saving all video+sound frames to a single file) under 32-bit Linux. Expected hardware is ATI Radeon HD 3800 series card.

I would like to be able to capture analog video on the AVIVO connector.

Which SDK allows this?

google

sullivany677 — 2009-07-10T05:11:24 -05.00

Subcontracting for AMD/ATI

ilghiz — 2009-07-01T12:31:57 -05.00

Hi,

would like to be advised to whom can I can forward my question. Our company developed a lot of numerical software starting from sparse/dence/compressed linear system solvers, CFD and wave propargation and many others. Last year we port a lot of our software to NVIDIA GPUs (I can provide 4 reference links from NVIDIA corporate site to our site).

We can use our 17 years software development experience to considerably improve ACML that will compete with MKL and beat most of CUDA enabled BLAS/LAPACK and other scientific libraries.

It would be very kind if somebody can forward this message or my contacts to some executives in AMD for discussion.

Sincerely,

Ilgis Ibragimov

Dr. Ilgis Ibragimov

Vice-President

Elegant Mathematics Ltd.

+49-163-7414473

30%-70% of phenom were actually developed in india ??

biocoat — 2009-07-01T05:14:14 -05.00

30% - 70% of Barcelona, Shanghai and Istanbuldoes? anyone know anything about that?

is that true?

http://www.cxotoday.com/India/News/AMD_India_Center_Develops_30-70_of_Processors/551-102762-912.html

new genration

shark74 — 2009-06-24T11:55:10 -05.00

hello

my name is Ahmed Hashim and I have new ideas for computer design

and I want to work for AMD

I may be short in the technical experience but I never run out ideas

and my ideas is more like logic develop for general design

so you can use my ideas and your experience to make another

generation of computer built in new rules

and for your consideration I have so many ideas for every computer

device

I tried the last month to contact with your company so i begin with

custom service and they guide my to research and development

offices and I sent so many fax's and their is no respond

and I cant make an international phone call

The that I tried to use my ideas is that i had old one that been done

like the sold stat Intel drive I thought in it long ago to use memory instead

of hard disk but they did it rung

and increase Intel processor grid to decrease heat

and connect ram to processor directly to increase speed

and connect sata primary drive to the main chipset

but it didn't happen yet

I cant put my ideas in here in public

but I can to any one from AMD

please I am series

my email is

shark_masry@yahoo.com

thank you

How to get a NDA access & how much it costs?

blackshard — 2009-06-23T17:34:02 -05.00

Hi all, I'm developing an utility for AMD Turion Processor for Windows/Linux, allowing to tweak core voltage and FID/DID and other options.

I based my works on document #41256 Bios and Kernel Developer Guide For AMD 11h Family Processors.

I see in the documentation some references to document #40683 AMD Family 11h Processor Electrical Datasheets and document #40182 AMD Voltage Regulator Specification, but i can't find any of those documents.

I see that an NDA agreement is needed to gain access to those documents, so I ask how can I get an NDA and how much it costs?

Thank you.

Measuring DMA Activity

elesueur — 2009-06-22T21:54:39 -05.00

Hi,

I have several Opteron test machines. I would like to profile some code, and at the same time measure the amount of DMA activity happening in the system.

The DMA would be caused by both network and disk IO.

I see in the Bios & Kernel Developers guide that there is a PMU event (ECh - probe responses and upstream requests). I can measure the number of requests generated by upstream devices (like network or disk controller separately from display refresh requests) but that doesn't tell me the size of each request.

Has anyone tried to measure the rate of DMA activity in an opteron system before?

How to increase processor speed upto 7 Ghz to 11 GHz.(May be 21 GHz)

vijaydidmca — 2009-06-19T06:47:18 -05.00

Note: Pls give attention, that after reading this blog, if you are interested for more details than you can give me your e-mail id so that i can give you that one. You may have some problems with graphics in this blog because of editor problem, if you want more clear graphics and details than mail your email id:

My contacts:

vijaydidmca@yahooj.com

v.tiwari@parasonglobal.com

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Increase Processor speed

A digital system might be converted into a decimal system.
a digital system has two voltage levels:
valtage levels: 0 volts and 5 volts.
the bit 0 represents 0 volts and bit 1 represents 5 volts.
in ascii there is boundation that 7 pulses will be needed to represent a alphanumeric or a symbol.
if a pulse needs 2 seconds to be execute,then 7 pulses will be needed 7 * 2 = 14 seconds.
so to execute a alphanumeric or to execute a symbol , processor need 14 seconds.

now consider a decimal system:

there will be 10 voltage levels in a decimal system suppose: 0,2,4,6,8,10,12,14,16,18,20 volts.
now instead of 7 pulses ( as in case of a digital system ) , only two or three pulsed will be needed to represent a number.speed is 2 * 2 = 4 sec. or 2 * 3 = 6 sec.
in this way we can find a processor 3 or 4 times faster than the present processors.

note: the quality of picture may decrease,but this is affordable where speed is more important than pictures.Or we can use a digital system to Process pictures and can use
a different system (say decimal) to calculate values.

why don't we try to make computer as wise as human by using decimal system, the only sytem that is understandable to human.

I think at last industries will have to move towards decimal system.

my contact if any suggetions:

name: vijay

contact: 09823855353

email: v.tiwari@parasonglobal.com or vijaydidmca@yahoo.com

india.

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Processor Speed

In digital system 7 bits are required to represent any symbol. For example suppose + 5 volts is used to represent binary 1 and 0 volts for binary 0.

Y axis (volts)
^
|10 volt
|                          1 0    1   1   0 0    1
|5 volt               ___     ______         ___     ~0 nSec
|_____________|__|__|_____|_____|__|____________________________>
( 0,0 )            5nS 5nS 5nS 5nS 5nS 5nS 5nS    X axis (Time in nSec)

a. Diagram showing need of 7 pulses in orthodox digital system.

7 bits ASCII code “1011001” is required to represent symbol “Y”.

Suppose one pulse needed 5 nono sec (refer to diagram a.). Then 7 pulses will need

7 × 5 nSec = 35 nSec.

Now compare this system with “Decimal” system.

In digital or ASCII system seven ( 2 power 7 = 128 symbols) pulses are needed.

In decimal system only three ( 10 power 3 = 1000 symbols) pulses will be needed to represent any symbol. For example suppose 0 volt represents decimal symbol 0, similarly + 5 volt for decimal symbol 1, +10 volt for 2, +15 volt for 3, + 20 volt for 4, + 25 volt for 5, +30 volt for 6, + 35 volt for 7, +40 volt for 8 and + 45 volt for decimal symbol 9 (just like 0 volt represents binary bit 0 and + 5 volt represents binary bit 1 in digital system).

Now the system will take ˜ 0 nSec for moving from voltage level 0 volt to voltage level + 45 volts. (Because in maths term If fluctuation from voltage level 0 to + 5volt takes ˜ 0 nSec then fluctuation from voltage level 0 to + 45 volts will also take ˜ 0 nSec.).

Just keep in mind that here symbol “~” means “very nearly equal to”.

Please refer to diagram b.

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Y axis (Volts)

b. Diagram showing need of only 3 pulses in unorthodox decimal system.

Diagram shows that only 3 pulses are required to represent any symbol in decimal system. Suppose Three symbols (say “327” is needed to represent “Y” in decimal system. See diagram b. ). Thus time needed to Process any symbol in any decimal system is 3 × 5 nSec = 15 nSec.

A system 2.33 times faster than orthodox digital system. But carefully notice that with 3 bits in decimal system we can process 10 power 3 = 1000 symbols. On the other hand with 7 bits in digital system we can represent only 2 power 7 = 128 symbols. If we limit the number of symbols to 100, then in decimal system only two voltage levels or signs will be needed, thus the time needed to represent any symbol will be 2 × 5 nSec = 10 nSec. In this way we will get a system 3.5 times faster than the digital system.

So that in decimal system we can assume processor speed up to 6 GHz to 10 GHz. Far better that orthodox digital system ( 2.5 GHz to 3 GHz ).

The way will be not easy because we will have to shift all flip-flops, shift registers, counters, encoders, decoders, ALU units, multiplexers, and many other components to work with decimal system rather than digital system. The only thing to do is make them working with 10 voltage levels rather than 2.

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Orthodox Digital (ASCII) Table.

Digital coding Symbol

01000001 A

01000010 B

01000011 C

…… ……

01011010 Z

Unorthodox Decimal Table

Decimal coding Symbol

345 A

346 B

347 C

…… ……

401 Z

Summary:

This is the day when we click and starts staring at the screen, because data is too large and speed is too slow. Or the instructions are so deeply nested with each other that Processor gets tired by running through them or gets halted. So think ahead and think differently. Ultimately we will have to move towards any other option other than “machine language”, important is who starts first.

One day when the data will become over large or the instructions will be over nested then the Processor will have to say “sorry! I can’t”.

Be remember:

“Ostrich puts his neck into a pit and thinks that lion will not come. But the lion comes”.

If any advice or suggestions then pls contact:

Vijay S. Tiwari.

MCA.

Contact:

vijaydidmca@yahoo.com

v.tiwari@parasonglobal.com

Region: India.

Note: Pls pay attention, that graphics are not clear because of editor problem if you want more clear graphics and details than you can give me your e-mail id so that i can give you more precise graphics and details:

My contacts:

vijaydidmca@yahooj.com

v.tiwari@parasonglobal.com

One person suggested me why we can't take hexa decimal system instead of decimal so that we can get more speed.

"my answer is yes we can take it also. one most important thing is that why we can't take 128 voltage levels, one for each symbol (remember ASCII has 128 symbols). so that we can get speed upto 18 GHz to 21 GHz."

now some entertainment:

1. where does hardware and software meats with each other?

2. can you write the world's most simple software?The answer is no,infact no one can write it.how and why?

For answers visit my site:

http://vstiwari.webs.com